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參數(shù)資料
| 型號： | HIP7020AB |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO8 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HIP7020AB |
7
on the bus is minimized by the bus interface filtering and
control circuitry of the Bus Transceiver IC.
High Current may exist during noise interference and bus
arbitration conditions on the bus. To limit instantaneous cur-
rent direction change and minimize the level of fluctuating
current caused by these conditions, a series resistance is
used in the bus output of the HIP7020. (See Figure 1). A
small resistor, R
E
, from the BUS OUT pin to the bus module
connection forces a distribution of bus current between
transmitting modules and provides load stability to the IC.
The HIP7020 maintains a uniform and consistent bus wave-
form having specific transition times and propagation delays
to preserve a J1850 analog data stream. Transmitted bus
data is encoded by a HIP7010 Byte Level IO or HIP7030
J1850 microcontroller, (see Figure 1) where “1s” and “0s”
are defined by the length of time in which the bus voltage is
high or low. Precise waveform control is necessary for a
receiving node to accurately decode the difference between
“1s” and “0s” by the time duration of high levels and low lev-
els on the bus. In order to retain bus data integrity, digital
information to be transmitted on the bus is wave shaped and
amplitude controlled in the Bus Transceiver. The transmitted
signal output to the J1850 Bus is a waveform with uniform
edge control and precisely defined voltage levels.
Bus Current and Voltage Control
The Bus Transceiver has a Wave Shaped Voltage Reference
which controls both the Voltage-to-Current Converter and
the Bus Voltage Driver, Q1. The Voltage-to-Current Con-
verter supplies a limited current feed to the collector of Q1.
Together this provides the function of a Voltage Controlled
Current Driver which controls the bus voltage drive level
while supplying limited current to drive the bus load.
Wave Shaped Voltage Reference, V
REF
The output of the Wave Shaped Voltage Reference is a uni-
form signal which is a scaled waveform of the desired bus
signal and is shown as V
REF
in Block Diagram. This signal
controls the output current driver and is the input to the Volt-
age-to-Current Converter. The internal reference voltage,
V
REF
is isolated from the J1850 Bus and is totally unaffected
by the signal conditions on the bus. This isolation provides
superior Bus stability in the vehicle environment. The bus
drive control interface maintains the integrity of the V
REF
waveform supplied to the bus. This is done without feedback
control which is inherently susceptible to oscillation.
Voltage-to-Current Converter
The Voltage-to-Current Converter generates a current, I
BO
which is proportional to the Wave Shaped Voltage Reference
magnitude and wave shape. This is the maximum current
that can be supplied to the bus and is limited to a value of
30mA typical.
Voltage Controller Current Driver
The Voltage Controller Current Driver, Q1, is the device
which controls the amount of the available current which will
be sourced out to the bus as determined by the Voltage Ref-
erence and allowed by the Voltage-to-Current Converter.
When the Bus voltage is below the Voltage Reference, Q1
allows more current to be sourced out to the J1850 Bus; until
the Bus voltage and the Voltage Reference match or until the
maximum current limit is reached as set by the Voltage-to-
Current Converter.
When the Bus voltage is above the Voltage Reference, Q1
allows less current sourced out to the J1850 Bus; until the
Bus voltage and the Voltage Reference match or until zero
current is being sourced from Q1.
Bus Output Waveform
The bus output waveform shown in Figure 5 is controlled by
the internal Wave Shaper and has a tightly controlled rise
and fall time with rounded corners. The rise/fall times, t
r
and
t
f
, are defined between V
BOL
and V
BOH
.
Constant Propagation Time Delay
There is a constant propagation time delay from TX signal
going high or low to the BUS OUT signal (measured at
3.875V). The propagation time delay signals are shown in
Figure 6. The timing to reach the 50% voltage level of the
bus signal from the start of TX input going high is t
DTXHBO
.
The propagation time delay from the start of TX input going
low is t
DTXLBO
.
The BUS IN input signals, as shown in Figure 6, are
characterized by the V
BIH
and V
BIL
specifications which
include hysteresis. There is a constant propagation delay for
the Bus to RX receive channel of the Bus Transceiver. The
received propagation delay times are t
DRXON
and t
DRXOFF
as measured in reference to the 50% voltage level on the ris-
ing or falling edge of the BUS IN input signal to the rising or
falling edge of the RX output signal.
HIP7020
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7020AP | 制造商:Harris Corporation 功能描述: |
| HIP7030A0 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
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