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參數(shù)資料
| 型號： | HIP7010B |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | J1850 Byte Level Interface Circuit |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO14 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 106K |
| 代理商： | HIP7010B |
4
Serial Interface Timing
(See Figure 1- Figure 7) T
A
= -40
o
C to +125
o
C, V
DD
= 5V
DC
±
10%, Unless Otherwise Specified
NUMBER
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNITS
-
-
Operating Frequency
2
8
12
MHz
-
-
Input CLK Duty Cycle
40
50
60
%
(1)
t
CYC
SCK Cycle Time
-
1.0
-
MHz
(2)
t
LEAD
SACTIVE Lead Time
Before Status/Control Transfer
450
750
850
ns
Before Data Transfer
1150
1225
1300
ns
(3)
t
LAG
SACTIVE Lag Time
After Status/Control Transfer
650
750
850
ns
After Data Transfer
1250
1300
1400
ns
(4)
t
SCKH
Clock (SCK) HIGH Time
450
500
550
ns
(5)
t
SCKL
Clock (SCK) LOW Time
450
500
550
ns
(6)
t
DVSCK
Required Data In Setup Time (SIN to SCK)
-
10
50
ns
(7)
t
SCKDX
Required Data In Hold Time (SIN after SCK)
-
-10
40
ns
(8)
t
DZDA
Data Active from High Impedance Delay (SACTIVE to SOUT Active)
-10
10
-
ns
(9)
t
DADZ
Data Active to High Impedance Delay (SACTIVE to SOUT High
Impedance)
-
10
40
ns
(10)
t
DVSCK
Data Out Setup Time (
SOUT to SCK
)
375
475
-
ns
(11)
t
DXSCK
Data Out Hold Time (SOUT after SCK)
375
475
-
ns
(12)
t
RISE
Output Rise Time (0.3V
DD
to 0.7V
DD
, C
L
= 100pF)
15
75
150
ns
(13)
t
FALL
Output Fall Time (0.7V
DD
to 0.3V
DD
, C
L
= 100pF)
7
25
75
ns
(14)
t
STATH
Required STAT Pulse Width
-
20
75
ns
(15)
t
RDYH
Required RDY Pulse Width
-
20
75
ns
t
RESETL
Required RESET Pulse Width
-
20
75
ns
(16)
t
SACTIVE
SACTIVE Delay from RDY (IDLE = V
SS
)
1150
1750
2450
ns
SACTIVE Delay from STAT (FTU = 0)
5
285
900
ns
(17)
t
RDYSCK
Required RDY Removal Time Prior to Last SCK for Short RDY
-
25
100
ns
(18)
t
SCKRDY
Required RDY Hold Time after Last SCK for Long RDY
-
0
100
ns
(19)
t
REC
Required SERIAL Recovery Time (Minimum Time after SACTIVE
Until Next RDY/STAT)
-
675
750
ns
f
SLOW
Slow clock detect frequency limit
20
80
200
KHz
NOTE:
1. All parameters are specifications of the HIP7010 component not of a system. Parameters specified as “Required” (i.e., t
STATH
) refer to
the requirements of the HIP7010. If a “Required” pulse width is specified as 75ns maximum, that implies that 75ns is the maximum width
that any HIP7010 device will require. Therefore, a system that provides a
minimum
pulse width of 75ns will satisfy this
maximum
requirement.
HIP7010
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