
2-324
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
The r
DS(ON)
is different for the two previous equations even
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 15 shows the gate drive where the
upper gate-to-source voltage is approximately V
CC
less the
input supply. For +5V main power and +12VDC for the bias,
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12VDC. A logic-level MOSFET is a good choice
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V
CC
.
Rectifier CR1 is a clamp that catches the negative inductor
voltage swing during the dead time between the turn off of
the lower MOSFET and the turn on of the upper MOSFET.
parasitic MOSFET body diode from conducting. It is
acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but
efficiency might drop one or two percent as a result. The
diode's rated reverse breakdown voltage must be greater
than twice the maximum input voltage.
Linear Controller Pass Transistor Selection
The main criteria for selection of a pass transistor for the
linear regulator is package selection for efficient removal of
heat. The power dissipated in a linear regulator is:
Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.
Additionally, if selecting a bipolar NPN transistor, insure the
gain (h
fe
) at the minimum operating temperature and given
collector-to-emitter voltage is sufficiently high as to deliver
the worst-case steady state current required by the GTL
output, when the transistor is driven with the minimum
guaranteed DRIVE3 output current. For example, operating
at ‘T’ junction temperature, 3.3V input, and 1.5V output
(V
CE
= 1.8V), the NPN’s gain should satisfy the following
equation:
(
)
DRIVE3
P
UPPER
I
------------------------------------------------------------
2
r
IN
×
V
×
I
----------------------------------------------------
V
×
t
×
F
S
×
+
=
P
LOWER
I
---------------------------------------------------------------------------------
2
r
IN
×
V
V
–
(
)
×
=
+12V
PGND
HIP6028
GND
LGATE
UGATE
PHASE
V
CC
+5V OR LESS
NOTE:
V
GS
≈
V
CC
-5V
NOTE:
V
GS
≈
V
CC
Q1
Q2
+
-
FIGURE 15. OUTPUT GATE DRIVERS
CR1
P
LINEAR
I
O
V
IN
V
OUT
–
(
)
×
=
h
fe
I
steady
----------------------------------------------------------
state
–
>
HIP6028