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參數(shù)資料
| 型號： | HIP6028 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Advanced PWM and Dual Linear Power Control with Integrated ACPI Support Interface |
| 中文描述： | 先進(jìn)的雙PWM和線性電源控制集成接口ACPI支持 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 140K |
| 代理商： | HIP6028 |
2-321
A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components in the
converter. Note that capacitors C
IN
and C
OUT
could each
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. The power plane
should support the input power and output power nodes.
Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit
layers for small signal wiring. The wiring traces from the
control IC to the MOSFET gate and source should be sized
to carry 1A currents. The traces for V
OUT2
need only be
sized for 0.2A. Locate C
OUT2
close to the HIP6028 IC.
PWM Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller. Apply the methods and
considerations to both PWM controllers.
Figure 12 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The reference
voltage level is the DAC output voltage for the PWM
controller. The error amplifier output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
IN
at the PHASE node.
The PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at F
LC
and a zero at F
ESR
. The DC gain of the modulator is
simply the input voltage, V
IN
, divided by the peak-to-peak
oscillator voltage,
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
internal to the HIP6028 and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with an acceptable 0dB
crossing frequency (f
0dB
) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f
0dB
and 180 degrees
.
The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 12.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
V
OUT1
Q1
Q2
C
SS
+12V
C
VCC
VCC
VIN2
L
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT1
C
OUT1
CR1
L
C
IN
V
OUT3
+5V
IN
FIGURE 11. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
KEY
HIP6028
SS
PGND
LGATE
UGATE
PHASE
DRIVE3
GND
OCSET
+3.3V
IN
Q3
L
C
OUT2
V
OUT2
VOUT2
R
OCSET
C
OCSET
FIGURE 12. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
-
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6028
Z
IN
DRIVER
DETAILED FEEDBACK COMPENSATION
PHASE
V
E/A
+
+
-
Z
IN
F
LC
L
O
2
π
C
O
×
×
---------------------------------------
=
F
ESR
O
-----------------------------------------
=
HIP6028
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相關(guān)代理商/技術(shù)參數(shù) |
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