參數(shù)資料
型號(hào): HIP6015CB
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor
中文描述: SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO20
封裝: PLASTIC, MS-013AC, SOIC-20
文件頁(yè)數(shù): 10/12頁(yè)
文件大小: 203K
代理商: HIP6015CB
10
the largest component of power dissipation for the MOSFET.
Switching losses also contribute to the overall MOSFET
power loss (see the equations below). These equations
assume linear voltage-current transitions and are
approximations. The gate-charge losses are dissipated by the
HIP6015 and do not heat the MOSFET. However, large gate-
charge increases the switching interval, t
SW
, which increases
the upper MOSFET switching losses. Ensure that the
MOSFET is within its maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
Standard-gate MOSFETs are normally recommended for
use with the HIP6015. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute
gate-to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
CC
. The boot capacitor, C
BOOT
,
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V
D
) when the Schottky diode, D2,
conducts. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V
CC
.
Figure 10 shows the upper gate drive supplied by a direct
connection to V
CC
. This option should only be used in
converter systems where the main input voltage is +5V
DC
or
less. The peak upper gate-to-source voltage is approximately
V
CC
less the input supply. For +5V main power and +12V
DC
for the bias, the gate-to-source voltage of Q
1
is 7V. A
logic-level MOSFET is a good choice for Q
1
under these
conditions.
Schottky Selection
Rectifier D
2
conducts when the upper MOSFET Q
1
is off. The
diode should be a Schottky type for low power losses. The
power dissipation in the Schottky rectifier is approximated by:
In addition to power dissipation, package selection and
heatsink requirements are the main design tradeoffs in
choosing the Schottky rectifier. Since the three factors are
interrelated, the selection process is an iterative procedure.
The maximum junction temperature of the rectifier must
remain below the manufacturer’s specified value, typically
125
o
C. By using the package thermal resistance
specification and the schottky power dissipation equation
(shown above), the junction temperature of the rectifier can
be estimated. Be sure to use the available airflow and
ambient temperature to determine the junction temperature
rise.
P
COND
= I
O2
r
DS(ON)
D
P
SW
= 1/2 I
O
V
IN
t
SW
F
S
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the switching interval, and
F
S
is the switching frequency.
+12V
HIP6015
GND
UGATE
PHASE
BOOT
V
CC
+5V OR +12
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
V
G-S
V
CC
- V
D
C
BOOT
D
BOOT
Q
1
D
2
+
-
+ V
D
-
+12V
HIP6015
GND
UGATE
PHASE
BOOT
V
CC
+5V OR LESS
Q
1
+
-
IGURE 10. UPPER GATE DRIVE - DIRECT V
CC
DRIVE OPTION
D
2
NOTE:
V
G-S
V
CC
-5V
P
COND
= I
0
x V
f
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
, and
V
f
is the Schottky forward voltage drop
HIP6015
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