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參數(shù)資料
| 型號： | HIP4081IP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 功率晶體管 |
| 英文描述： | 80V/2.5A Peak, High Frequency Full Bridge FET Driver |
| 中文描述： | 2.6 A FULL BRDG BASED MOSFET DRIVER, PDIP20 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 216K |
| 代理商： | HIP4081IP |
16
Timing Diagrams
NOTE:
6. ALI and/or BLI may be high after t1, whereupon the ENABLE pin
may also be brought high.
FIGURE 35.
NOTE:
7. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin
to go through one complete cycle (transition order is not impor-
tant). If the ENABLE pin is low after the undervoltage circuit is
satisfied, the ENABLE pin will initiate the 10ms time delay during
which the IN+ and IN- pins must cycle at least once.
FIGURE 36.
V
DD
DIS
ALI, BLI
8.5V TO 10.5V (ASSUMES 5% RESISTORS)
1.7V
12V, FINAL VALUE
V
DD
DIS
LDEL
=10ms
t1
t2
8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)
12V, FINAL VALUE
5.1V
HIP4081
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