參數(shù)資料
型號: HIP4081IB
廠商: HARRIS SEMICONDUCTOR
元件分類: MOSFETs
英文描述: System Basic Chips (SBC); Package: PG-DSO-28; Transceiver: Fault-tollerant CAN ISO 11898 - 3; Voltage Regulator Output: 120 mA; Watchdog: Window Watchdog; Quiescent Current<sub> (max.): &lt; 85 &#181;A (5V on); Standby current: &lt; 500 &#181;A (5V on)
中文描述: 2.6 A FULL BRDG BASED MOSFET DRIVER, PDSO20
文件頁數(shù): 15/18頁
文件大?。?/td> 216K
代理商: HIP4081IB
15
Supplemental Information for HIP4080
and HIP4081 Power Application
The HIP4080 and HIP4081 H-Bridge Driver ICs require
external circuitry to assure reliable start-up conditions of the
upper drivers. If not addressed in the application, the
H-bridge power MOSFETs may be exposed to shoot-
through current, possibly leading to MOSFET failure. Follow-
ing the instructions below will result in reliable start-up.
HIP4081
The HIP4081 has four inputs, one for each output. Outputs
ALO and BLO are directly controlled by input ALI and BLI.
By holding ALI and BLI low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 33. As the V
DD
/V
CC
supply ramps from zero
up, the DIS voltage is below its input threshold of 1.7V due to
the R1/R2 resistor divider. When V
DD
/V
CC
exceeds approxi-
mately 9V to 10V, DIS becomes greater than the input
threshold and the chip disables all outputs. It is critical that
ALI and BLI be held low prior to DIS reaching its threshold
level of 1.7V while V
DD
/V
CC
is ramping up, so that shoot
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
HIP4080
The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a com-
parator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.
However, keeping both lower MOSFETs off can be accom-
plished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 34. Pulling
LDEL to V
DD
will indefinitely delay the lower turn-on delays
through the input comparator and will keep the lower MOS-
FETs off. With the lower MOSFETs off and the chip enabled,
i.e., DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+/IN- switch a full cycle while LDEL
is held high, to avoid shoot-through. This start-up procedure
can be initiated by the supply voltage and/or the chip enable
command by the circuit in Figure 33.
FIGURE 33.
FIGURE 34.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1 BHB
BHI
DIS
V
SS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
V
DD
V
CC
ALS
BHS
ALO
AHS
AHO
3.3K
R2
ENABLE
R1
15K
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1 BHB
BHI
DIS
V
SS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
V
DD
V
CC
ALS
BHS
ALO
AHS
AHO
3.3K
R2
R1
15K
ENABLE
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1 BHB
HEN
DIS
V
SS
OUT
IN+
HDEL
IN-
LDEL
AHB
BHO
BLO
BLS
V
DD
V
CC
ALS
BHS
ALO
AHS
AHO
100K
RDEL
RDEL
V
DD
0.1
μ
F
2N3906
V
DD
ENABLE
V
DD
56K
8.2V
56K
100K
HIP4081
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