VIN = 0V, 4V - 0.01 ±1.0 - ±1.0 A REFERENCE INPU" />
參數(shù)資料
型號: HI9P5701K-5
廠商: Intersil
文件頁數(shù): 7/12頁
文件大?。?/td> 0K
描述: CONV A/D 6BIT 30MSPS 18-SOIC
標(biāo)準(zhǔn)包裝: 40
位數(shù): 6
采樣率(每秒): 30M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 300mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC W
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極
4
Analog Input Bias Current, IB
VIN = 0V, 4V
-
0.01
±1.0
-
±1.0
A
REFERENCE INPUTS
Total Reference Resistance, RL
250
370
-
235
-
Reference Resistance Tempco, TC
-
+0.266
-
/oC
DIGITAL INPUTS
Input Logic High Voltage, VIH
2.0
-
2.0
-
V
Input Logic Low Voltage, VIL
-
0.8
-
0.8
V
Input Logic High Current, IIH
VIN = 5V
-
1.0
-
1.0
A
Input Logic Low Current, IIL
VIN = 0V
-
1.0
-
1.0
A
Input Capacitance, CIN
-
7
---
pF
DIGITAL OUTPUTS
Output Logic Sink Current, IOL
VO = 0.4V
3.2
-
3.2
-
mA
Output Logic Source Current, IOH
VO = 4.5V
-3.2
-
-3.2
-
mA
Output Leakage, IOFF
CE2 = 0V
-
±1.0
-
±1.0
A
Output Capacitance, COUT
CE2 = 0V
-
5.0
-
pF
TIMING CHARACTERISTICS
Aperture Delay, tAP
-
6
---
ns
Aperture Jitter, tAJ
-
30
---
ps
Data Output Enable Time, tEN
(Note 3)
-
12
20
-
20
ns
Data Output Disable Time, tDIS
(Note 3)
-
11
20
-
20
ns
Data Output Delay, tOD
(Note 3)
-
14
20
-
20
ns
Data Output Hold, tH
(Note 3)
5
10
-
5
-
ns
POWER SUPPLY REJECTION
Offset Error PSRR,
VOS
VDD = 5V ±10%
-
±0.1
±1.0
-
±1.5
LSB
Gain Error PSRR,
FSE
VDD = 5V ±10%
-
±0.1
±1.0
-
±1.5
LSB
POWER SUPPLY CURRENT
Supply Current, IDD
fS = 20MHz
-
50
60
-
75
mA
NOTE:
3. Parameter guaranteed by design or characterization and not production tested.
Electrical Specifications
VDD = +5.0V; VREF+ = +4.0V; VREF- = VSS = GND; fS = Specified Clock Frequency at 50% Duty Cycle;
CL = 30pF; Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
25oC
(NOTE 3)
0oC TO 70oC
UNITS
MIN
TYP
MAX
MIN
MAX
HI-5701
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