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7-1858
Bipolar/Unipolar Input Ranges
The inputs can accept either unipolar or bipolar input volt-
ages with each physical channel’s mode being independent
of other physical channels. Bipolar or unipolar options are
chosen by programming the bipolar/unipolar (B/U) bits of the
Channel Configuration Registers (CCR). Programming the
logical channels for either unipolar or bipolar operation does
not change any of the input signal conditioning. The inputs
are differential, and as a result are referenced to the voltage
on the V
INL
input. For example, if V
INHX
is +3.75V and logi-
cal channel X is configured for unipolar operation with a gain
of 1 and a V
REF
of +2.5V, the input voltage range on the
V
INLX
input is +1.25V to +3.75V. If V
INLX
is +1.25V and logi-
cal channel X is configured for bipolar mode with gain of 1
and a V
REF
of +2.5V, the analog input range on the V
INHX
input is -1.25V to +3.75V.
Multiplexer
The input multiplexer is a fully differential 8 channel device
controlled by the internal microsequencer. Any number of
inputs, up to 8, can be scanned and both the number of phys-
ical channels scanned and the scanning order are controlled
by the users programming of the Channel Configuration Reg-
ister (CCR). The output of the multiplexer feeds the input to
the Programmable Gain Instrumentation Amplifier (PGIA).
External Multiplexers
For interfacing the HI7188 to external multiplexers several
output pins are available. These pins include MXC, A
2,
A
1
and A
0
. Refer to Figure 9. The MXC pulse is active high dur-
ing the modulator and integrating filter reset pulse. The pulse
width is typically 14.6
μ
s with LNR disabled and 54.6
μ
s with
LNR enabled. This signal can be used to “break before
make” an external multiplexer. Referring to Figure 9, the data
conversion time involves the actual input channel A/D con-
version while the calibration time involves data calibration
and coding of the conversion results. The address pins A
2,
A
1
and A
0
describe the
logical
address which is currently
being converted. The user can utilize these output pins to
drive external multiplexer address pins.
The main critical issue is the external multiplexer output
must switch and settle to 0.00153% (16 bits) of the final
value during the MXC reset pulse and prior to Data Integra-
tion or data errors will occur. The input must be stable only
during the data integration period but can be changed during
the calibration period.
Programmable Gain Instrumentation Amplifier
The Programmable Gain Instrumentation Amplifier (PGIA)
allows the user to interface low level sensors and bridges
directly to the HI7188. The PGIA has 4 selectable gain
options of 1, 2, 4, and 8. The gain of each physical channel
is independent of other physical channels and is program-
mable by writing the G1 and G0 bits in the Channel Configu-
ration Registers (CCR).
Differential Reference Input
The reference inputs, V
RHI
and V
RLO
, provide a differential
reference input capability. V
RHI
must always be greater than
V
RLO
for proper operation of the device. The common mode
range for these differential inputs is from AV
SS
to AV
DD
and
the nominal differential voltage (V
REF
= V
RHI
- V
RLO
) is
+2.5V. Larger values of V
REF
can be used with minor degra-
dation in performance. Smaller values of V
REF
can also be
used but performance will be degraded since the system
noise is larger relative to the LSB size. The full scale range
of the HI7188 is defined as:
FSR
BIPOLAR
= 2 x V
REF
/GAIN
FSR
UNIPOLAR
= V
REF
/GAIN
The reference inputs provide a high impedance dynamic
load similar to the analog inputs. For proper circuit operation
these pins must be driven by low impedance circuitry. Refer-
ence noise outside of the band of interest will be removed by
the digital filter but excessive reference noise inside the band
of interest will degrade performance.
V
CM
Input
The V
CM
input is the internal reference voltage for the
HI7188 analog circuitry and should always be tied to the
midpoint of the AV
DD
and AV
SS
supplies. This point pro-
vides a common mode input voltage for the internal opera-
tional amplifiers and must be driven from a low noise, low
impedance source if it is not tied to analog ground. Failure to
do so will result in degraded HI7188 performance. It is rec-
ommended that V
CM
be tied to analog ground when operat-
ing off of AV
DD
= +5V and AV
SS
= -5V supplies. V
CM
also
determines the headroom at the upper and lower ends of the
power supplies which is limited by the common mode input
range where the internal operational amplifiers remain in the
linear, high gain region of operation.
Sigma Delta Modulator
The sigma delta modulator is a fourth order modulator which
converts the differential analog signal into a series of one bit
outputs. The 1’s density of this data stream provides a digital
representation of the analog input. Figure 10 shows a simpli-
fied block diagram of the analog modulator front end of a
Sigma-Delta A/D Converter. The input signal V
IN
comes into
a summing junction (the PGIA in this case) where the previ-
ous modulator output is subtracted from it. The resulting sig-
nal is then integrated and the output of the integrator goes
into the comparator. The output of the comparator is then fed
back via a one bit DAC to the summing junction. The feed-
back loop forces the average of the fed back signal to be
equal to the input signal V
IN
.
C
ADDR
A
2, 1, 0
DATA
CONVERSION CALIBRATION
CHAN
SWITCH
t
MXC
MXC
DATA
CONVERSION
VALID LOGICAL ADDRESS
VALID LOGICAL ADDRESS
FIGURE 9. CHANNEL SWITCHING TIMING
HI7188