參數(shù)資料
型號： HI7188
廠商： Intersil Corporation
英文描述： 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System
中文描述： 8通道，16位，精度高，Σ-ΔA / D轉換子系統(tǒng)
文件頁數(shù)： 7/22頁
文件大?。?/td> 156K
代理商： HI7188
7-1853
Output Three-State Leakage
Current, I
OZ
V
OUT
= 0V, +5V (Note 7)
-
1
10
μ
A
Digital Output Capacitance, C
OUT
(Note 2)
-
10
-
pF
TIMING CHARACTERISTICS
SCLK Minimum Cycle Time, t
SCLK
(Notes 2, 7)
200
-
-
ns
SCLK Minimum Pulse Width, t
SCLKPW
(Notes 2, 7)
60
-
-
ns
CS to SCLK Precharge Time, t
PRE
(Notes 2, 7)
50
-
-
ns
Data Setup to SCLK Rising Edge
(Write), t
DSU
(Notes 2, 7)
50
-
-
ns
Data Hold from SCLK Rising Edge
(Write), t
DHLD
(Notes 2, 7)
0
-
-
ns
Data Read Access from Instruction
Byte Write, t
ACC
(Notes 2, 7)
-
-
40
ns
Read Bit Valid from SCLK Falling
Edge, t
DV
(Notes 2, 7)
-
-
40
ns
Last Data Transfer to Data Ready
Inactive, t
DRDY
(Notes 2, 7)
-
50
-
ns
RESET Low Pulse Width t
RESET
(Notes 2, 7)
100
-
-
ns
RSTI/O Low Pulse Width t
RSTI/O
(Notes 2, 7)
100
-
-
ns
MUX High Pulse Width t
MUX
(Notes 2, 7)
14
μ
s
CADDR Valid to MUX High
(Notes 2, 7)
75
ns
Oscillator Clock Frequency
(Notes 2, 7)
-
3.6864
-
MHz
Output Rise/Fall Time
(Notes 2, 7)
-
-
30
ns
Input Rise/Fall Time
(Notes 2, 7)
-
-
1
μ
s
POWER SUPPLY CHARACTERISTICS
IAV
DD
AV
DD
= +5V, OSC
1
= 3.6864MHz (Note 3)
-
1.8
3.0
mA
IAV
SS
AV
SS
= -5V, OSC
1
= 3.6864MHz (Note 3)
-
1.8
3.0
mA
IDV
DD
DV
DD
= +5V, SCLK = 4MHz
-
2.0
4.0
mA
Power Dissipation, Active PD
A
AV
DD
= +5V, AV
SS
= -5V, SLP = ‘0’
(Notes 3, 9)
-
28
50
mW
Power Dissipation, Sleep PD
S
AV
DD
= +5V, AV
SS
= -5V, SLP = ‘1’
(Notes 3, 9)
-
5
-
mW
PSRR (
V
supply
= 0.25V)
PSRR = 20log (
V
supply
/
V
OS
) (Note 3)
-
75
-
dB
NOTES:
2. Parameter guaranteed by design or characterization, not production tested.
3. DC PSRR is measured on all supplies individually and applies to both Bipolar and Unipolar Input Ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 1, R
1
= 10k
, C
L
= 50pF (Includes Stray and Jig Capacitance).
8. For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz.
9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>).
Electrical Specifications
AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
RHI
= +2.5V, V
RLO
= AGND, V
CM
= AGND, PGIA Gain = 1,
OSC
IN
= 3.6864MHz, Bipolar Input Range Selected
(Continued)
PARAMETER
TEST CONDITION
-40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
HI7188
相關PDF資料
PDF描述
HI7188IN 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System
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相關代理商/技術參數(shù)
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