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參數(shù)資料
| 型號： | HI5762 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual 10-Bit, 60MSPS A/D Converter(雙路、10位采樣速率為60MSPS的A/D轉(zhuǎn)換器) |
| 中文描述： | 雙10位，60MSPS的A / D轉(zhuǎn)換器（雙路，10位采樣速率為60MSPS的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 107K |
| 代理商： | HI5762 |
3-14
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ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
I/Q Channel Crosstalk
I/Q Channel Crosstalk is a measure of the amount of
channel separation or isolation between the two A/D
converter cores contained within the dual converter
package. The measurement consists of stimulating one
channel of the converter with a fullscale input signal and
then measuring the amount that signal is below, in dBc, a
fullscale signal on the opposite channel.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (t
AP
)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
AJ
)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
H
)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
OD
)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
LAT
)
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus
following the 6th cycle of the clock after the analog sample is
taken. This is due to the pipeline nature of the converter
where the analog sample has to ripple through the internal
subconverter stages. This delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 6 sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
HI5762
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5762/4IN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| HI5762/6IN | 功能描述:CONV A/DDUAL 10BIT 60MSPS 44MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI5762/6INZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC W/ANNEAL 44L MQFP IN A/D 10B 60MSPS VREF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI5762_10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 10-Bit, 60MSPS A/D Converter with Internal Voltage Reference |
| HI5762EVAL2 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVAL MODULA DVIC TYPE HI5762 AMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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