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參數(shù)資料
| 型號： | HI5762/6IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | CONV A/DDUAL 10BIT 60MSPS 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 60M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 670mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極；8 個差分，雙極 |
13
FN4318.3
January 22, 2010
The analog input can be DC coupled (see Figure 17) as long
as the inputs are within the analog input common mode
voltage range (0.25V
≤ VDC ≤ 4.75V).
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on
AC-coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 18 may be used with a
single-ended AC-coupled input.
Again, with VRIN connected to VROUT, if VIN is a 1VP-P
sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at positive
full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ - I/QIN-=+0.5V)
and will be at negative full scale when I/QIN+ is equal to
VDC - 0.5V (I/QIN+-I/QIN- = -0.5V). Sufficient headroom must
be provided such that the input voltage never goes above +5V
or below AGND. In this case, VDC could range between 0.5V
and 4.5V without a significant change in ADC performance.
The simplest way to produce VDC is to use the DC bias source,
I/QVDC, output of the HI5762.
The single ended analog input can be DC-coupled (see
Figure 19) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on
AC-coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single-ended source may give better overall system
performance if it is first converted to differential before
driving the HI5762.
Sampling Clock Requirements
The HI5762 sampling clock input provides a standard
high-speed interface to external TTL/CMOS logic families.
In order to ensure rated performance of the HI5762, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL/CMOS levels.
Performance of the HI5762 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of
20 cycles at a sample rate above 1MSPS must be
performed before valid data is available.
Supply and Ground Considerations
The HI5762 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DVCC3, which can be powered from a 3.0V or 5.0V
supply. This allows the outputs to interface with 3.0V logic if
so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5762 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High-Speed A/D
Converters” (AN9214) for additional considerations when
using high-speed converters.
I/QIN+
I/QVDC
I/QIN-
HI5762
VIN
-VIN
R
C
VDC
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
I/QIN+
I/QIN-
HI5762
VIN
VDC
R
FIGURE 18. AC COUPLED SINGLE-ENDED INPUT
I/QIN+
I/QIN-
HI5762
VDC
R
C
VIN
VDC
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
HI5762
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