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參數(shù)資料
| 型號： | HI5710AJCQ |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | Circular Connector; No. of Contacts:32; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:18-32 RoHS Compliant: No |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MQFP-48 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HI5710AJCQ |
4-1543
(CLK/16). A 14-bit counter is also counting the CLK/16
signal and when the 14-bit counter reaches the end of its
count range the carry out from the counter is used to gate off
or mask the CLK/16 power-up calibration pulses.
The time required for the power-up calibration process to be
completed after the above five conditions has been met can
be calculated using the following equation:
t
Power-Up Cal
= (2
4
x 2
14
)/(f
CLK
) = 2
18
/f
CLK
.
For example, if the sample clock frequency is 20MHz, the
time required for the power-up calibration process to be
completed, after the above five conditions has been met, is
t
Power-Up Cal
= 2
18
/f
CLK
= 2
18
/20x10
6
= 262,144/20 x 10
6
,
t
Power-Up Cal
= 13.1ms.
Auto Calibration Pulse Generation Function
The auto calibration pulse generator provides the user with
the choice of internal or external periodic calibration pulse
generation following the completion of the power-up calibra-
tion process. The selection of internal or external periodic
calibration pulse generation is made through the use of the
SEL control input pin (pin 17). Setting the SEL control input
pin high (logic 1) selects the internal periodic calibration
pulse generation function. Setting the SEL control input pin
low (logic 0) selects the external calibration pulse input pin
(CAL, pin 41).
For the case where the internal periodic calibration pulse
generation function has been chosen, SEL control input pin
high, the auto calibration pulse generator periodically gener-
ates calibration pulses internally so that calibration is per-
formed constantly without the need to provide calibration
input pulses from an external source. These periodic calibra-
tion pulses are derived from the divided-by sixteen sample
clock (CLK/16). The CLK/16 signal drives a 24-bit counter
which generates a carry-out that is used as the internal cali-
bration pulse. The time between calibration pulses when
using the internal auto calibration pulse generator can be
calculated using the following equation:
t
Internal Cal Pulse
= (2
4
x 2
24
)/(f
CLK
) = 2
28
/f
CLK
.
For example, if the sample clock frequency is 20MHz, the
time between internal auto calibration pulses is:
t
Internal Cal Pulse
= 2
28
/f
CLK
= 2
28
/20x10
6
=
268,435,456/20 x 10
6
,
t
Internal Cal Pulse
= 13.4s.
Since a calibration is completed once every seven
calibration pulses, the time required to complete a
calibration cycle is:
t
Internal Cal Cycle
= (7 x 2
28
)/f
CLK
.
Therefore, if the sample clock frequency is 20MHz, the inter-
nal calibration cycle is:
t
Internal Cal Cycle
= (7 x 2
28
)/20 x 10
6
= 93.95s.
It should be noted that this method of periodic calibration
may not be acceptable if the fixing of the lower five output
bits during the calibration (see the discussion below on
external calibration pulse input function) would cause
problems since the calibration is executed asynchronously
without regard to the analog input signal.
External Calibration Pulse Input Function
If the auto calibration pulse generation function cannot be
used then periodic calibration can be performed by providing
externally input calibration pulses to the CAL input pin
(pin 41) and setting the SEL control input pin (pin 17) low.
Refer to Figure 3, External Calibration Pulse Timing
Diagram, for details on the required timing of the externally
supplied calibration pulses.
A setup time of 10ns or longer is required for the CAL input
and it must stay low for at least one sample clock (CLK)
period. Calibration starts when the falling edge of the exter-
nally supplied calibration pulse, input to the CAL pin, is
detected. One calibration is completed in 11 sample clock
cycles. Seven sample clock cycles after the falling edge of
the externally supplied calibration pulse is detected, the
calibration circuit takes exclusive possession of the lower
comparators, D0 through D4, for four sample clock cycles.
During this time, the D0 through D4 outputs are latched with
the previous data (cycle seven data). The upper 5 bits, D5
through D9, will operate as usual during the calibration.
The calibration must be done when the part is first powered up,
if the sampling frequency changes, when the supplies vary
more than 100mV or when (V
RT
- V
RB
) changes more than
200mV. Figure 4 shows several possible external calibration
pulse timing schemes where the calibration is performed
outside the active video interval by using the video sync signal
as the externally supplied CAL input. It is not necessary to
calibrate as often as these figures show, these are only design
ideas. It is also possible to use only the power-up calibration
function by leaving the SEL control input pin (pin 17) low and
fixing the CAL input pin (pin 41) either high or low. Note,
however, that using only the power-up calibration function will
require the above restrictions on the sample frequency and the
fluctuation range of the power supply voltage and the
reference voltage differential be maintained.
Initiating/Re-Initiating Power-up Calibration Function
The power-up calibration function can be initiated/re-initiated
after the power supply voltage and the reference voltages
are stabilized by using the CE (pin 24) or RESET (pin 15)
control input pins. This might prove useful in a situation
where the turn-on characteristics of the power supply and
reference voltages is unstable/indeterminate or where the
sequence of power-up does not meet the required conditions
stated earlier.
Power, Grounding, and Decoupling
To reduce noise effects, keep the analog and digital grounds
separated. Bypass both the digital and analog V
DD
pins to
their respective grounds with a ceramic 0.1
μ
F capacitor
close to the input pin. A larger capacitor (1
μ
F to 10
μ
F)
should be placed somewhere on the PC board for low fre-
quency decoupling of both analog and digital supplies.
The analog supply should be present before the digital supply
to reduce the risk of latch-up. The digital supply can run from
+3.3V or +5V. A +3.3V supply generates less radiated noise at
the digital outputs, but results in less drive capability. The
specifications do not change with digital supply levels.
Remember, the digital outputs will only swing to DV
DD
.
HI5710A
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HI5710EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HI5714/4CB | 功能描述:IC ADC 8-BIT 40MSPS 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI5714/4CBS2503 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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