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參數(shù)資料
| 型號(hào)： | HI3-7159A-5Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 5-1/2 DIGIT 28-PDIP |
| 標(biāo)準(zhǔn)包裝： | 13 |
| 位數(shù)： | 5.5 位 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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12
Therefore values of RINT should be between 200k and
400k
. The exact value of RINT may be altered to get the
exact integrator swing desired after choosing a standard
capacitor value for CINT.
The most critical component in any integrating A/D converter
is the integrating capacitor, CINT. For a converter of this
resolution, it is imperative that this component perform as
closely to an ideal capacitor as possible. Any amount of
leakage or dielectric absorption will manifest itself as
linearity errors. For this reason CINT must be a high quality
polypropylene capacitor. Use of any other type may degrade
performance. The value of CINT is determined by the
magnitude of the desired maximum integrator output voltage
swing as shown below:
Solving for CINT yields:
where VSWING is the maximum output voltage swing of the
integrator, VIN is the full scale input voltage (VIN HI -VIN LO)
to the converter (equal to 2 X VREF), and tINT is the time in
which VIN is integrated. The best results are achieved when
the maximum integrator output voltage is made as large as
possible, yet still less than the nonlinear region in the vicinity
of the power supply limit. A full scale output swing of about
3V provides the greatest accuracy and linearity.
NOTE:
The integrator is auto-zeroed to the voltage at VIN LO.If VIN
LO is negative with respect to AGND, the integrator will have | VIN LO
| less headroom for positive input voltages (inputs where VIN
HI -VIN LO > 0). If VIN LO is positive with respect to AGND, the inte-
grator will have | VIN LO | less headroom for negative input voltages
(inputs where VIN HI -VIN LO < 0). In most applications VIN LO is at
or near AGND and the above equations will be adequate. In applica-
tions where VIN LO may be more than 0.1V away from AGND, it
should be included in the integrator swing considerations. The follow-
ing formula combines all the above considerations:.
Gain Error Adjustments
While the HI-7159A has a very linear transfer characteristic
in both the positive and negative directions, the slope of the
line is slightly greater for negative inputs than for positive.
This results in the transfer characteristic shown in Figure 9.
One end point of this curve, typically the positive side, can
be adjusted to zero error by trimming the reference voltage.
The other (negative) side will have a xed gain error. This
error can be removed in software by multiplying all negative
readings by a scale factor, determined by dividing the ideal
full scale reading (-200,000 counts) by the actual full scale
reading when VIN = -2.00000V.
CREF Guard Pins
Depending on the polarity of the input signal, either the
negative or the positive terminal of the reference capacitor
will be connected to AGND to provide the correct polarity for
reference deintegration. In systems where VREF LO is tied
to analog ground, the reference capacitor is effectively
shifted down by | VREF | for positive input voltages, and is
not shifted at all for negative input voltages. This shift can
cause some charge on the reference capacitor to be lost
due to stray capacitance between the reference capacitor
leads and ground traces or other fixed potentials on the
board. The reference voltage will now be slightly smaller for
positive inputs. This difference in reference voltages for
positive and negative inputs appears as rollover error.
The HI-7159A provides two guard ring outputs to minimize
this effect. Each guard ring output is a buffered version of the
voltage at its respective CREF pin. If the traces going to the
CREF pins and under CREF itself are surrounded by their
corresponding guard rings, no charge will be lost as CREF is
moved. Figure 10 shows two slightly different patterns. The
rst one is for capacitors of symmetrical construction, the
second is for capacitors with outside foils (one end of the
capacitor is the entire outside.
V
SWING
V
IN
() t
INT
()
R
INT
() C
INT
()
-------------------------------------
=
C
INT
V
IN
() t
INT
()
R
INT
() V
SWING
()
-----------------------------------------------
=
V
IN LO
V
IN HI
V
IN LO
–
() 10 000
,
()
R
INT
() C
INT
() f
OSC
()
-----------------------------------------------------------------------
–
3V
≤
200,000
100,000
000,000
-100,000
-200,000
OUTPUT
COUNT
-2
INPUT (V)
-200,012
COUNTS
-1
0
1
2
FIGURE 9. TYPICAL HI-7159A TRANSFER CHARACTERISTIC
GUARD
CREF-
(5)
CREF-
(6)
CREF+
(7)
CREF+ GUARD
(8)
GUARD
(5)
(6)
(7)
GUARD
(8)
HI -7159A
FIGURE 10. TYPICAL GUARD RING LAYOUT
CREF-
CREF+
HI-7159A
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