參數(shù)資料
型號(hào)： HI3-674AKN-5
廠商： Intersil
文件頁(yè)數(shù)： 5/18頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 67KSPS 28-SBDIP
標(biāo)準(zhǔn)包裝： 13
位數(shù)： 12
采樣率（每秒）： 67k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 720mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 75°C
安裝類(lèi)型： 通孔
封裝/外殼： 28-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 28-PDIP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；2 個(gè)單端，雙極
13
FN3096.6
August 7, 2008
Conversion Start
A conversion may be initiated as shown in Table 3 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-X74A Timing Specifications, Convert Mode.
This variety of HI-X74A control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 3.
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or re-initiate a conversion while
STS is high.
Reading the Output Data
The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high
and CS low. At that time, data lines become active according
to the state of inputs 12/8 and AO. Timing constraints are
illustrated in Figure 4.
The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active simultaneously, for interface
to a 12-bit or 16-bit data bus. The AO input is ignored.
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by AO. This allows an 8-bit data bus
to be connected as shown in Figure 5. AO is usually tied to
the least significant bit of the address bus, for storing the
HI-X74A output in two consecutive memory locations. (With
AO low, the 8 MSBs only are enabled. With AO high, 4 MSBs
are disabled, bits 4 through 7 are forced low, and the 4 LSBs
are enabled). This two byte format is considered “l(fā)eft justified
data,” for which a decimal (or binary!) point is assumed to
the left of byte 1:
Further, AO may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 5 will never be enabled at the
same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (tDD + tHS)
before STS goes low. See Figure 4.
BYTE 1
BYTE 2
XX
0
MSB
LSB
See HI-X74A Timing Specifications for more information.
FIGURE 3. CONVERT START TIMING
See HI-X74A Timing Specifications for more information.
FIGURE 4. READ CYCLE TIMING
CE
CS
R/C
AO
STS
DB11-DB0
tSSC
tSRC
tHEC
tHSC
tSAC
tHAC
tDSC
tC
HIGH IMPEDANCE
tHRC
CE
CS
R/C
AO
STS
DB11-DB0
HIGH IMPEDANCE
tSSR
tSRR
tSAR
tHS
tHD
tHL
tDD
tHAR
tHRR
tHSR
DATA
VALID
HI-574A, HI-674A
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