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參數(shù)資料
| 型號(hào)： | HI3-5700J-5 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 8-Bit, 20 MSPS Flash A/D Converter |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 746K |
| 代理商： | HI3-5700J-5 |
4-1499
HI-5700
Applications Information
Voltage Reference
The reference voltage is applied across the resistor ladder
between V
REF
+ and V
REF
-. In most applications, V
REF
- is
simply tied to analog ground such that the reference source
drives V
REF
+. The reference must be capable of supplying
enough current to drive the minimum ladder resistance of
235
over temperature.
The HI-5700 is specified for a reference voltage of 4.0V, but
will operate with voltages as high as the V
DD
supply. In the
case of 4.0V reference operation, the converter encodes the
analog input into a binary output in LSB increments of
(V
REF
+ - V
REF
-)/256, or 15.6mV. Reducing the reference
voltage reduces the LSB size proportionately and thus
increases linearity errors. The minimum practical reference
voltage is about 2.5V. Because the reference voltage
terminals are subjected to internal transient currents during
conversion, it is important to drive the reference pins from a
low impedance source and to decouple thoroughly. Again,
ceramic and tantalum (0.01
μ
F and 10
μ
F) capacitors near
the package pin are recommended. It is not necessary to
decouple the
1
/
4
R,
1
/
2
R, and
3
/
4
R tap point pins for most
applications.
It is possible to elevate V
REF
- from ground if necessary. In
this case, the V
REF
- pin must be driven from a low
impedance reference capable of sinking the current through
the
resistor
ladder.
Careful
recommended.
decoupling
is
again
Digital Control and Interface
The HI-5700 provides a standard high speed interface to
external CMOS and TTL logic families. Two chip enable
inputs control the three-state outputs of output bits D0
through D7 and the Overflow (OVF) bit. As indicated in the
Truth Table, all output bits are high impedance when CE2 is
low, and output bits D0 through D7 are independently
controlled by CE1.
Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local group disturbances.
Therefore, an external bus driver is recommended.
Clock
The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the “Theory of Operation” section. The Auto
Balance
φ
1 half cycle of the clock may be reduced to
approximately 20ns; the Sample
φ
2 half cycle may be varied
from a minimum of 25ns to a maximum of 5
μ
s.
Signal Source
A current pulse is present at the analog input (V
IN
) at the
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feedthrough in the capacitor array. It varies with the
amplitude of the analog input and the converter’s sampling
FIGURE 15. TEST CIRCUIT
1/4R
V
DD
V
IN
V
REF
-
OVF
CE2
CE1
CLK
V
REF
+
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D7
D6
D5
D4
D3
D2
D1
D0
GND
3/4R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AV
DD
AGND
AV
DD
AV
DD
AGND
AV
DD
1
/
2
R
AGND
AGND
50
10
μ
F
0.01
μ
F
DIGITAL
V
DD
OUTPUT
PINS
OUTPUT
PINS
TO ANALOG GND
TO ANALOG +5V
CLOCK INPUT
DIGITAL
GROUND
100
+9V TO +12V
+9V TO +12V
HA-5033
ANALOG
GROUND
0.01
μ
F
0.01
μ
F
0.01
μ
F
0.01
μ
F
0.01
μ
F
+5V
10
μ
F
ANALOG
SIGNAL
INPUT
10
μ
F
10
μ
F
10
μ
F
10
μ
F
ANALOG
V
DD
(+5V)
PRECISION
DC
REFERENCE
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