參數(shù)資料
型號(hào)： HI1260JCQ
廠商： INTERSIL CORP
元件分類： DAC
英文描述： Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter
中文描述： PARALLEL, 8 BITS INPUT LOADING, 0.0016 us SETTLING TIME, 8-BIT DAC, PQFP48
封裝： PLASTIC, MQFP-48
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 166K
代理商： HI1260JCQ
10-6
TABLE 1. INPUT CORRESPONDING TABLE
INPUT CODE
OUTPUT VOLTAGE
MSB
LSB
1
1
1
1
1
1
1
1 V
CC
+ V
OFFSET
1
0
0
0
0
0
0
0 V
CC
+ V
OFFSET
-0.5V
0
0
0
0
0
0
0
0 V
CC
+ V
OFFSET
-1.0V
Standard Circuit Design Data
T
A
= 25
o
C, AV
CC
= DV
CC
= 5.0V, AGND = DGND = 0.0V
PARAMETER
SYMBOL
TEST CONDITIONS
NOTES
MIN
TYP
MAX
UNITS
Crosstalk Among R, G and B
CT
D/A OUT: 1V
P-P
R
L
> 10k
C
L
< 20pF
f
DATA
= 7MHz
f
CLK
= 14MHz
See Figure 5
-
-40
-35
dB
Glitch Energy
GE
V
SET
– AGND = 0.87V
R
L
> 10k
f
CLK
= 1MHz
Digital Ramp Output
See Figure 6
Note 5
-
30
-
pV/s
Rise Time
t
r
V
SET
-AGND = 0.87V
See Figure 4
Note 6
-
5.5
-
ns
Fall Time
t
f
Note 6
-
5.0
-
ns
Settling Time
t
SET
-
1.6
-
ns
NOTE:
5. Observe the glitch which is generated when the digital input varies as follows:
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
6. The time required for the D/A OUT to arrive at 90% of its final value from 10%.
1
1
1
–
–
–
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Test Circuits and Waveforms
FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUIT
DV
CC
DGND
D1
D2
D8
D1 - D8
D1 - D8
D1 - D8
8 (R)
8 (G)
8 (B)
39 - 42
44 - 47
1 - 8
9 - 16
HI1260
33
31
29
27
25
24
23
20
R
OUT
G
OUT
B
OUT
A
VCC
V
REF
V
SET
V
V
+
-
33
μ
F
3K
19, 37, 43
18
CLK TTL LEVEL
CLK
HI1260
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