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參數(shù)資料
| 型號(hào)： | HI1175JCB |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8-BIT FLASH 20MSPS 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 300 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 60mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
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12
Static Performance Definitions
Offset, full scale, and gain all use a measured value of the
internal voltage reference to determine the ideal plus and
minus full scale values. The results are all displayed in
LSBs.
Offset Error (EOB)
The first code transition should occur at a level 1/2 LSB
above the bottom reference voltage. Offset is defined as the
deviation of the actual code transition from this point. Note
that this is adjustable to zero.
Full Scale Error (EOT)
The last code transition should occur for a analog input that
is 11/2 LSBs below full scale. Full scale error is defined as
the deviation of the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB. The converter is guaranteed to have no
missing codes.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI1175. A low
distortion sine wave is applied to the input, it is sampled, and
the output is stored in RAM. The data is then transformed
into the frequency domain with a 1024 point FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is -0.5dB down from fullscale
for all these tests. The distortion numbers are quoted in dBc
(decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to fullscale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency
excluding DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
where:
VCORR = 0.5dB.
Total Harmonic Distortion
This is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the 2nd and 3rd
harmonic component respectively to the RMS value of the
measured input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component. If the harmonics are buried in the noise floor it is
the largest peak.
Full Power Input Bandwidth
Full power bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the reference voltage. The bandwidth given is measured at
the specified sampling frequency.
Timing Definitions
Sampling Delay (tSD)
Sampling delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
This is the RMS variation in the sampling delay due to
variation of internal clock path delays.
Data Latency (tLAT)
After the analog sample is taken, the data on the bus is
available after 2.5 cycles of the clock. This is due to the
architecture of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input by 2.5 cycles.
Output Data Delay (tD)
Output Data Delay is the delay time from when the data is
valid (rising clock edge) to when it shows up at the output
bus. This is due to internal delays at the digital output.
HI1175
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI1175JCB-T | 功能描述:CONV A/D 8BIT 20MSPS 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI1175JCP | 制造商:Harris Corporation 功能描述: |
| HI1176 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS, Flash A/D Converter |
| HI1176_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS, Flash A/D Converter |
| HI1176-EV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS, Flash A/D Converter |
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