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參數(shù)資料
| 型號(hào)： | HI-8282J-44 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| 中文描述： | 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大小： | 448K |
| 代理商： | HI-8282J-44 |
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FUNCTIONAL DESCRIPTION
DATA
BUS
PIN
FUNCTION
CONTROL
DESCRIPTION
If enabled, an internal connection
is made passing 429DO and
to the receiver logic inputs
429DO
BDO5
SELF TEST
0 = ENABLE
RECEIVER 1
DECODER
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO6
1 = ENABLE
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
BDO7
-
-
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
BDO8
-
-
RECEIVER 2
DECODER
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BDO9
1 = ENABLE
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
BD10
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
BD11
-
-
INVERT
XMTR
PARITY
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
BD12
1 = ENABLE
BD13
XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14
RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
CONTROL WORD REGISTER
The HI-8282 contains 10 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to
flip flop provides options to the user as follows:
. Each
CWSTR
THERECEIVERS
ARINCBUSINTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specificationrequiresthefollowingdetectionlevels:
The HI-8282 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition(4.75Vsupplyand13vsignallevel).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls,thechiprejectsthedata.
STATE
ONE
NULL
ZERO
DIFFERENTIALVOLTAGE
+6.5Volts to +13Volts
+2.5Volts to -2.5Volts
-6.5Volts to -13Volts
BYTE 2
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ARINC
BIT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ARINC
BIT
13
12
11
10
9
31
30
32
1
2
3
4
5
6
7
8
BYTE 1
HOLT INTEGRATED CIRCUITS
4-31
相關(guān)PDF資料 |
PDF描述 |
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| HI-8382JT | ARINC 429 DIFFERENTIAL LINE DRIVER |
| HI-8382UT | ARINC 429 DIFFERENTIAL LINE DRIVER |
| HI-8382CM-01 | ARINC 429 DIFFERENTIAL LINE DRIVER |
| HI-8382CM-03 | ARINC 429 DIFFERENTIAL LINE DRIVER |
| HI-8382 | 256 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8282JF-44 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282JT-44 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282JTF-44 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282PQI | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
| HI-8282PQT | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER |
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