參數(shù)資料
型號： HFA3863IN96
廠商： INTERSIL CORP
元件分類： 無繩電話/電話
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64
封裝： 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64
文件頁數(shù)： 11/39頁
文件大小： 305K
代理商： HFA3863IN96
4-11
Scrambling is done by division with a prescribed polynomial
as shown in Figure 9. A shift register holds the last quotient
and the output is the exclusive or of the data and the sum of
taps in the shift register. The transmit scrambler seed for the
long preamble or for the short preamble can be set with
CR48 or CR49.
For the 1Mbps DBPSK data rates and for the header in all
rates using the long preamble, the data coder implements
the desired DBPSK coding by differential encoding the serial
data from the scrambler and driving both the I and Q output
channels together. For the 2Mbps DQPSK data rate and for
the header in the short preamble mode, the data coder
implements the desired coding as shown in the DQPSK
Data Encoder table. This coding scheme results from
differential coding of dibits (2 bits). Vector rotation is
counterclockwise although bits 6 and 7 of configuration
register CR 1 can be used to reverse the rotation sense of
the TX or RX signal if desired.
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and
CCK spread spectrum signals. The modulator is capable of
automatically switching its rate where the preamble is
DBPSK modulated, and the data and/or header are
modulated differently. The modulator can support date rates
of 1, 2, 5.5 and 11Mbps. The programming details to set up
the modulator are given at the introductory paragraph of this
section. The HFA3863 utilizes Quadraphase (I/Q)
modulation at baseband for all modulation modes.
In the 1Mbps DBPSK mode, the I and Q Channels are
connected together and driven with the output of the
scrambler and differential encoder. The I and Q Channels
are then both multiplied with the 11-bit Barker word at the
spread rate. The I and Q signals go to the Quadrature
upconverter (HFA3724) to be modulated onto a carrier.
Thus, the spreading and data modulation are BPSK
modulated onto the carrier.
For the 2Mbps DQPSK mode, the serial data is formed into
dibits or bit pairs in the differential encoder as detailed
above. One of the bits from the differential encoder goes to
the I Channel and the other to the Q Channel. The I and Q
Channels are then both multiplied with the 11-bit Barker
word at the spread rate. This forms QPSK modulation at the
symbol rate with BPSK modulation at the spread rate.
Transmit Filter Description
To minimize the requirements on the analog transmit
filtering, the transmit section shown in Figure 11 has an
output digital filter. This filter is a Finite Impulse Response
(FIR) style filter whose passband shape is set by tap
coefficients. This filter shapes the spectrum to meet the
radio spectral mask requirements while minimizing the peak
to average amplitude on the output. To meet the particular
spread spectrum processing gain regulatory requirements in
Japan on channel 14, an extra FIR filter shape has been
included that has a wider main lobe. This increases the 90%
power bandwidth from about 11MHz to 14MHz. It has the
unavoidable side effect of increasing the amplitude
modulation, so the available transmit power is compromised
by 2dB when using this filter (CR 11 bit 5).
CCK Modulation
For the CCK modes, the spreading code length is 8 complex
chips and based on complementary codes. The chipping
rate is 11Mchip/s. The following formula is used to derive the
CCK code words that are used for spreading both 5.5 and
11Mbps:
(LSB to MSB), where c is the code word.
The terms:
1,
2,
3, and
4 are defined below for
5.5Mbps and 11Mbps.
This formula creates 8 complex chips (LSB to MSB) that are
transmitted LSB first. The coding is a form of the generalized
Hadamard transform encoding where the phase
1 is added
PREAMBLE (SYNC)
128/56 BITS
SFD
16 BITS
SIGNAL FIELD
8 BITS
SERVICE FIELD
8 BITS
LENGTH FIELD
16 BITS
CRC16
16 BITS
HEADER
PREAMBLE
FIGURE 8. 802.11 PREAMBLE/HEADER
TABLE 4. DQPSK DATA ENCODER
PHASE SHIFT
DIBIT PATTERN (d0, d1)
d0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
FIGURE 9. SCRAMBLING PROCESS
Z
-1
Z
-2
Z
-3
Z
-4
Z
-5
Z
-6
Z
-7
XOR
SERIAL DATA
IN
XOR
SERIAL
DATA OUT
c
e
j
1
2
3
4
+
+
+
(
)
e
j
1
3
4
+
+
(
)
e
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1
2
4
+
+
(
)
,
e
j
1
4
+
(
)
e
j
1
2
3
+
+
(
)
e
j
1
3
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(
)
e
j
1
2
+
(
)
e
j
1
,
–
,
,
,
–
,
,
=
HFA3863
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