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3
Test Circuit
Application Information
Offset Adjustment
The HFA1103 allows for adjustment of the inverting input bias
current to null the output offset voltage. -I
BIAS
flows through
R
F
, so any change in bias current forces a corresponding
change in output voltage. The amount of adjustment is a
function of R
F
. With R
F
= 750
, the typical adjust range is
150mV. For offset adjustment connect a 10k
potentiometer
between pins 1 and 5 with the wiper connected to V-.
PC Board Layout
The frequency performance of these amplifiers depends a
great deal on the amount of care taken in designing the PC
board.
The use of low inductance components such as
chip resistors and chip capacitors is strongly
recommended, while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
μ
F) tantalum in parallel with a small value
chip (0.1
μ
F) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input. The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to pin 2, and connections to pin 2 should
be kept as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Evaluation Board
The HFA1100 series evaluation board may be used for the
HFA1103 with minor modifications. The evaluation board
may be ordered using part number HFA11XXEVAL. Please
note that an HFA1103 sample is not included with the
evaluation board and must be ordered separately.
The layout and schematic of the board are shown below:
Overshoot
V
OUT
= 2.0V Step
A
V
= +2, V
OUT
= 0 to 2V, +2V to 0V
V
OUT
= 2V to 0V
2X Overdrive
25
-
10
-
%
Slew Rate
25
-
600
-
V/
μ
s
0.1% Settling
25
-
9
-
ns
Overdrive Recovery Time
25
-
12
-
ns
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
Full
±
4.5
-
±
5.5
V
Supply Current (No Load)
25
-
11
16
mA
Full
-
-
23
mA
NOTES:
2. The residual sync is specified at the output of a doubly terminated circuit (see page 1 of this data sheet).
3. Since the HFA1103 has an open emitter NPN output stage, this measurement is only valid for positive values.
4. The -I
BIAS
current can be used to adjust the offset voltage to zero, but -I
BIAS
does not flow bidirectionally because the HFA1103 output stage
is an open emitter NPN transistor.
5. V
OS
includes the error contribution of I
BSN
at R
F
= 750
.
6. This is the minimum change in inverting input bias current when a BAL pin is connected to V- through a 50
resistor.
Electrical Specifications
V
SUPPLY
=
±
5V, A
V
= +2, R
F
= 750
, R
L
= 50
, Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
MIN
TYP
MAX
UNITS
V
OUT
R
IN
50
V
IN
DUT
R
G
750
R
F
750
R
L
50
+
-
FIGURE 1. TEST CIRCUIT
1
2
3
4
8
7
6
5
+5V
10
μ
F
0.1
μ
F
V
H
50
GND
GND
500
500
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
V
L
FIGURE 2. EVALUATION BOARD SCHEMATIC
HFA1103