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參數(shù)資料
| 型號(hào)： | HEF40162BP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-bit synchronous decade counter with synchronous reset |
| 中文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 166K |
| 代理商： | HEF40162BP |
January 1995
2
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
synchronous reset
HEF40162B
MSI
DESCRIPTION
The HEF40162B is a fully synchronous edge-triggered
4-bit decade counter with a clock input (CP), four
synchronous parallel data inputs (P
0
to P
3
), four
synchronous mode control inputs (parallel enable (PE),
count enable parallel (CEP), count enable trickle (CET)
and synchronous reset (SR)), buffered outputs from all
four bit positions (O
0
to O
3
) and a terminal count output
(TC).
Operation is synchronous and occurs on the LOW to HIGH
transition of CP. When PE is LOW, the next LOW to HIGH
transition of CP loads data into the counter from P
0
to P
3
.
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise no change occurs in the state of
the counter. TC is HIGH when the state of the counter is 9
(O
0
= O
3
= HIGH, O
1
= O
2
= LOW) and when CET is
HIGH. A LOW on SR sets all outputs (O
0
to O
3
and TC)
LOW on the next LOW to HIGH transition of CP,
independent of the state of all other synchronous mode
control inputs (CEP, CET and PE). Multistage
synchronous counting is possible without additional
components by using a carry look-ahead counting
technique; in this case, TC is used to enable successive
cascaded stages. CEP, CET, PE and SR must be stable
only during the set-up time before the LOW to HIGH
transition of CP.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
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| HEF40162BT | 4-bit synchronous decade counter with synchronous reset |
| HEF40163B | 4-bit synchronous binary counter with synchronous reset |
| HEF40163BN | 4-bit synchronous binary counter with synchronous reset |
| HEF40163BP | 4-bit synchronous binary counter with synchronous reset |
| HEF40163BT | 4-bit synchronous binary counter with synchronous reset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF40162BPN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| HEF40162BT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit synchronous decade counter with synchronous reset |
| HEF40162BTD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| HEF40162BTD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| HEF40163 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit synchronous binary counter with synchronous reset |
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