參數(shù)資料
型號： HE84770D
廠商： King Billion Electronics Co., Ltd.
英文描述： 8-bit Micro-controller
中文描述： 8位微控制器
文件頁數(shù)： 4/29頁
文件大?。?/td> 360K
代理商： HE84770D
King Billion Electronics Co., Ltd
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億
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股
份
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公
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HE84770D
HE80000 SERIES
August 7, 2006
This specification is subject to change without notice. Please contact sales person for the latest version before use.
Page 4 of 29
V1.2
Pin Name
Pin # I/O
Description
will turn on the key scan function.
8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The
function of the pad can be selected individually by mask options MO_LIO14[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[15..8]. The
function of the pad can be selected individually by mask options MO_LIO15[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The
function of the pad can be selected individually by mask options MO_LIO17[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, “1” must be outputted before reading.
50 ~ 81 O LCD COMMON Driver pads.
82
P
LCD Bias Voltage 1.
83
P
LCD Bias Voltage 2
84
P
LCD Bias Voltage 3
85
P
LCD Bias Voltage 4
86
P
LCD Bias Voltage 5.
87
I
LCD Drive Voltage Setting
88
P
Charge Pump Output..
89
O Charge Pump Capacitor Pin.
90
O Charge Pump Capacitor Pin.
91
O Charge Pump Capacitor Pin.
92
O Charge Pump Capacitor Pin.
93
O Charge Pump Capacitor Pin.
94
O Charge Pump Capacitor Pin.
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns
pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
96
I
Regulator Voltage Setting
97
O Reference Voltage Output. Fixed 0.9 Volt DC reference voltage
98
P
Power ground Input.
DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = ‘1’ and OP = ‘0’)
register to turn on DAC with VO output.
Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = ‘1’ and OP =
‘1’) to turn on DAC with DAO output as well as OP comparator.
Inverting input of OP Amp. Set the bit 0 of VOC register (OP = ‘1’) to turn on OP
comparator.
102
I
Non-inverting input of OP Amp.
103
O Output of OP Amp.
System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.
105, 106 O, External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’
PRT14[7..0]/
SEG[23:16]
26 ~ 33 B/
O
PRT15[7..0]/
SEG[15:8]
34 ~ 41 B/
O
PRT17[7..0]/
SEG[7:0]
42 ~ 49 B/
O
COM[31..0]
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
95
O
LGS1
LVAG
GND
VO
99
O
DAO
100
O
OPIN
101
I
OPIP
OPO
RSTP_N
104
I
FXO,
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