
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
HE84770
HE80000 SERIES
21.
Important Note
August 25, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
Page 28 of 30
V2.6E
1.
The LCD refresh cycles are:
32 COM : Refresh Cycle=~170Hz
48 COM : Refresh Cycle=~110Hz.
2.
To access any data ROM (DROM) of which address is larger than 64KB, users must update TPP first,
TPH 2nd and TPL lastly. Only follow this order, the pre-charge circuit of DROM will work correctly.
Since the Data ROM is a low speed ROM. 5us waiting time is necessary before LDV instruction is
executed to access the DROM. Note this 5us delay can’t be emulated in the developing tools (ICE and
KBIDS) and the 5us delay should be added by firmware.
3.
LCD driving circuit must be turn off before IC enters into sleep mode.
4.
Please bonds the TSTP_P, RSTP_N and PRTD[7:0] with test point on PCB (can be soldered and
probed) as you can. If necessary, some IC testing can be done on the PCB. The following figure is an
example (Testing point with through hole).
5.
LVP must small than 8.5 Volt. Otherwise IC may breakdown.
6.
The LCD voltage adjustment mechanism shall be reserved for LV5 voltage fine-tunes; since it’s possible
there is some variation in LV5 voltage due to IC manufacture process variation. User can use
variable-resistor to adjust the LV5 voltage or use some tools to detect the LV5 and then select a proper
resistor. Please refer to application note AN025 for the detailed description.
7.
Users must call the library “swap_page” in the file swappage.asm of AN029. The real IC register is different
from ICE4.x or ICE5.x. This subroutine makes sure that users can run on both real IC and ICE for page
swapping.
.area
swapping_variable(data)
_mapreg1:: .ds 1 ;store page register(R1Bh)
_mapreg2:: .ds 1 ;store page register(R1Ch)