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King Billion Electronics Co., Ltd
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HE83R123
HE80000 Series
March 13, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
14
V1.0E
Register Address
Field
Bit position Mode
Description
1: TC2 is enabled.
12.
Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by
abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option.
MO_WDTE Function
0
1
WDT disable
WDT enable
To use WDT function, “CLRWDT” instruction needs to be executed in every possible program path
when the program runs normally in order to clears the WDT counter before it overflows, so that the
program can operate normally. When abnormal conditions happen to cause the MCU to divert from
normal path, the WDT counter will not be cleared and reset signal will be generated.
WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is
same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in
Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock
has stopped.)
13.
Pulse-Width Modulation
The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to
proportional duty cycle of PWM output. PWM module shares the PWMC data register with
Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is
enabled, it generates signal with duty ratio in proportion to the DA value.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of