14
Self Test Function (Bits 5, 6)
Bit 6 of the Control Word Register
is used to initiate the self test
function. Results of the internal
self test are stored in bit 5 of the
Control Word. Bit 5 is a read only
bit where bit 5 = “1” indicates a
passed self test and bit 5 = “0”
indicates a failed self test.
Setting bit 6 to a logic 1 will start
the self test function. The built-in
self test function of the IC consists
of two internal routines which
exercises major portions of the IC
and illuminates all of the LEDs.
The first routine cycles the ASCII
decoder ROM through all states
and performs a checksum on the
output. If the checksum agrees
with the correct value, bit 5 is set
to “1.” The second routine
provides a visual test of the LEDs
using the drive circuitry. This is
accomplished by writing
checkered and inverse checkered
patterns to the display. Each
pattern is displayed for approxi-
mately 2 seconds.
During the self test function the
display must not be accessed. The
time needed to execute the self
test function is calculated by
multiplying the clock period by
262,144. For example, assume a
clock frequency of 58 KHz, then
the time to execute the self test
function frequency is equal to
(262,144/58,000) = 4.5 second
duration.
At the end of the self test function,
the Character RAM is loaded with
blanks, the Control Word Register
is set to zeros except for bit 5, and
the Flash RAM is cleared and the
UDC Address Register is set to all
ones.
Clear Function (Bit 7)
Bit 7 of the Control Word will
clear the Character RAM and the
Flash RAM. Setting bit 7 to a "1"
will start the clear function. Three
clock cycles (110
μ
s min. using
the internal refresh clock) are
required to complete the clear
function. The display must not be
accessed while the display is
being cleared. When the clear
function has been completed, bit
7 will be reset to a “0.” The ASCII
character code for a space (20H)
will be loaded into the Character
RAM to blank the display and the
Flash RAM will be loaded with
“0”s. The UDC RAM, UDC Address
Register, and the remainder of the
Control Word are unaffected.
Display Reset
Figure 7 shows the logic levels
needed to Reset the display. The
display should be Reset on Power-
up. The external Reset clears the
Character RAM, Flash RAM,
Control Word and resets the
internal counters. After the rising
edge of the Reset signal, three
clock cycles (110
μ
s min. using
the internal refresh clock) are
required to complete the reset
sequence. The display must not be
accessed while the display is
being reset. The ASCII Character
code for a space (20H) will be
loaded into the Character RAM to
blank the display. The Flash RAM
and Control Word Register are
loaded with all "0"s. The UDC
RAM and UDC Address Register
are unaffected. All displays which
operate with the same clock
source must be simultaneously
reset to synchronize the Flashing
and Blinking functions.
Mechanical and Electrical
Considerations
The HDSP-213X/-2179 is a 32 pin
dual-in-line package with 24
external pins, which can be
stacked horizontally and vertically
to create arrays of any size. The
HDSP-213X/-2179 is designed to
operate continuously from -55
°
C
to +85
°
C with a maximum of 20
dots ON per character. Illuminat-
ing all thirty-five dots at full
brightness is not recommended.
The HDSP-213X/-2179 is
assembled by die attaching and
wire bonding 280 LED chips and
a CMOS IC to a ceramic
substrate. A glass window is
placed over the ceramic substrate
creating an air gap over the LED
wire bonds. A second glass
window creates an air gap over
the CMOS IC. This package
construction makes the display
highly tolerant to temperature
cycling and allows wave soldering
and visual inspection of the IC.
Figure 7. Logic Levels to Reset the
Display.
Figure 8. Maximum Power Dissipation
vs. Ambient Temperature Derating
Based on T
J
MAX = 125
°
C.