- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371797 > HDMP-1536A Fiber-Optic Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | HDMP-1536A |
| 英文描述： | Fiber-Optic Transceiver |
| 中文描述： | 光纖收發(fā)器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 177K |
| 代理商： | HDMP-1536A |
4
Pin Name
TO_NODE[0]+
Pin
20
Pin Type Pin Description
O-PECL
In CDR at entry configuration, this pin is the Serial Output
(TO_LOOP+). In other configurations, this pin is wired to the hard disk.
O-PECL
In CDR at entry configuration, this pin is the Serial Output
(TO_LOOP–). In other configurations, this pin is wired to the hard disk.
I-PECL
Input from Transceiver IC to Cell 1.
I-PECL
Input from Transceiver IC to Cell 1.
O-PECL
Output to Transceiver IC from Cell 1.
O-PECL
Output to Transceiver IC from Cell 1.
I-PECL
In CDR at entry configuration, this pin is the Serial Input
(FM_LOOP+). In other configurations, this pin is wired to the hard disk.
I-PECL
In CDR at entry configuration, this pin is the Serial Input
(FM_LOOP–). In other configurations, this pin is wired to the hard disk.
I-LVTTL
Bypass pin for cell 1. In CDR at exit configuration, float to HIGH else
ground connect through a 1 K
resistor.
I-LVTTL
Bypass pin for cell 0. In CDR at exit configuration, float to HIGH else
ground connect through a 1 K
resistor.
I-LVTTL
Reference Clock Input for Clock and Data Recovery (CDR) circuit.
C
PLL cap pin. Connected to pin 13 with a 0.1 microFarad capacitor.
C
PLL cap pin. Connected to pin 12 with a 0.1 microFarad capacitor.
O-LVTTL
Signal Detect via envelope detect method. In CDR at entry and at exit
cases, detects signal on incoming cable respectively. Active High when
signal is detected.
If (FM_NODE[0]+ –FM_NODE[0]–) >= 400 mV peak-to-peak, SD = 1
If 400 mV >= (FM_NODE[0]+ –FM_NODE[0]–) >= 100 mV,
SD = unpredictable
If 100 mV >= (FM_NODE[0]+ –FM_NODE[0]–), SD = 0
S
6, 7, 11, 18, 19 Ground pins.
S
Analog Power Supply pin.
S
Cell 1 High Speed Output Pins Power Supply.
S
Cell 0 High Speed Output Pins Power Supply.
S
Logic Power Supply pins.
TO_NODE[0]–
21
FM_NODE[1]+
FM_NODE[1]–
TO_NODE[1]+
TO_NODE[1]–
FM_NODE[0]+
02
01
05
04
23
FM_NODE[0]–
24
BYPASS[1]–
08
BYPASS[0]–
17
REFCLK
CPLL1
CPLL0
SD[1]
SD[0]
14
12
13
09
16
GND
V
CC
A
V
CC
HS
15
03
22
10
V
CC
Table 3. Pinout
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1546A | IC-TRANSCEIVER |
| HDMP-1637A | 1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
| HDMP-1685A | 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel Interface |
| HDMP-2501 | Clock/Data Recovery |
| HDMP-2630B | Telecomm/Datacomm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
| HDMP-1636AG | 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。