參數(shù)資料
型號: HDMP-0421
英文描述: Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions(應用于光纖通道和判優(yōu)環(huán)路及其擴展的端口旁路電路)
中文描述: 端口旁路電路的光纖通道仲裁環(huán)路標準及其擴展(應用于光纖通道和判優(yōu)環(huán)路及其擴展的端口旁路電路)
文件頁數(shù): 9/12頁
文件大?。?/td> 177K
代理商: HDMP-0421
9
Figure 8. Setup for Measurement of Deterministic Jitter.
Figure 7. Setup for Measurement of Random Jitter.
70841B
PATTERN
GENERATOR
HDMP-0421
83480A
DIGITAL
COMMUNICATION
ANALYZER
70311A
CLOCK SOURCE
CLOCK
K28.7
REFCLK
TRIGGER
106.25 MHz
1062.5 MHz
RANDOM JITTER
± DATA
0011111000
2
± FM_NODE[0]
BYPASS-[0]
BYPASS-[1]
± TO_NODE[0]
CH 1/2
2
1/10
VARIABLE
DELAY
1.4
BIAS
N/C
106.25 MHz
70841B
PATTERN
GENERATOR
HDMP-0421
83480A
DIGITAL
COMMUNICATION
ANALYZER
70311A
CLOCK SOURCE
CLOCK
+K28.5 –K28.5
REFCLK
TRIGGER
106.25 MHz
1062.5 MHz
DETERMINISTIC JITTER
± DATA
2
± FM_NODE[0]
BYPASS-[0]
BYPASS-[1]
± TO_NODE[0]
CH 1/2
2
1/10
VARIABLE
DELAY
1.4
BIAS
N/C
106.25 MHz
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相關代理商/技術參數(shù)
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