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參數(shù)資料
| 型號： | HDD64M72D18RPW |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register |
| 中文描述： | DDR SDRAM內(nèi)存模塊512Mbyte（64Mx72bit），在32Mx8，4Banks，8K的參考依據(jù)。，184Pin與鎖相環(huán)內(nèi)存 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 171K |
| 代理商： | HDD64M72D18RPW |
HANBit
HDD64M72D18RPW
URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
CAPACITANCE
(V
DD
= min to max, V
DDQ
= 2.5V
to 2.7V, T
A
= 25
°
C, f = 100MHz)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)
C
IN1
-
12
pF
Input capacitance(CKE0,CKE1)
C
IN2
-
12
pF
Input capacitance(/CS0,/CS1)
C
IN3
-
11
pF
Input capacitance(CK0~/CK1)
C
IN4
-
12
pF
Input capacitance(DM0~DM8)
C
IN5
-
16
pF
Data & DQS input/output capacitance (DQ0 ~ DQ63,
DQS0~DQS8)
C
OUT1
-
16
pF
Data input/output capacitance (CB0~CB7))
DC CHARACTERISTICS
C
OUT2
-
16
pF
(Recommended operating condition unless otherwise noted, V
DD
= 2.5V, T =25
°
C)
version
-13A
pARAMETER
Symbo
l
TEST
Condition
-10A
-13B
Unit
Operating current
(One bank
active-Precharge)
I
DD0
t
RC
≥
t
RC
(min), t
CK=100MHz
for DDR200,133MHz for
DDR266A & DDR266B
DQ,DM and DQS inputs changing twice per clock
cycle Address and control inputs changing once per
clock cycle
1515
1695
1695
mA
Operating current
(One bankOperation)
I
DD1
One bank open, BL=4,Reads-Refer to the following
page for detailed test condition
1605
1875
1875
mA
Precharge
down
standby current
power-
I
DD2P
All banks idle, power-down mode
CKE
≤
V
IL
(max), t
CK=100MHz
for DDR200,133MHz for
DDR266A & DDR266B V
IN
= V
REF
for DQ,DQS and
DM
885
1020
1020
mA
Precharge Floating
standby current
I
DD2F
/CS
≥
V
IH
(min), All banks idle
CKE
≥
V
IH
(min), t
CK=100MHz
for DDR200,133MHz for
DDR266A & DDR266B
Address and control inputs changing once per clock
cycle V
IN
= V
REF
for DQ,DQS and DM
/CS
≥
V
IH
(min), All banks idle
CKE
≥
V
IH
(min), t
CK=100MHz
for DDR200,133MHz for
DDR266A & DDR266B Address and other control
inputs stable with keeping
≥
V
IH
(min) or
≤
V
IL
(max)
V
IN
= V
REF
for DQ,DQS and DM
1020
1155
1155
mA
Precharge Quiet
Standby current
I
DD2Q
975
1110
1110
Active power-down
Mode standby current
I
DD3P
One bank active; power-down mode;
CKE
≤
V
IL
(max), t
CK=100MHz
for DDR200,133MHz for
DDR266A & DDR266B V
IN
= V
REF
for DQ,DQS and
DM.
1020
1155
1155
mA
Active standby
current
I
DD3N
CS# >= VIH(min), CKE>=VIH(min)
one bank active, active
–
precharge, tRC=tRASmax
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B, DQ, DQS and DM inputs changing
twice per clock cycle Address and other control
inputs changing once per clock cycle
1110
1290
1290
mA
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| HDD64M72D18RW-13A | DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD64M72D18RW-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD64M72D18RW-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD64M72D18RWP-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD64M72D18W | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., with 184Pin-DIMM |
| HDD64M72D18W-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., with 184Pin-DIMM |
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