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參數(shù)資料
| 型號(hào)： | HDD32M72D9RPW-13A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx72bit），基于對(duì)32Mx8，4Banks 8K的參考。，184Pin - DIMM內(nèi)存的鎖相環(huán) |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大小： | 418K |
| 代理商： | HDD32M72D9RPW-13A |
HANBit
HDD32M72D9RPW
URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 1.0 (JUNE.2003)
COMMAND TRUTH TABLE
(V=Valid, X=Don
’
t Care, H=Logic High, L=Logic Low)
CK
E
n-1
Register
Extended MRS
H
X
Register
Mode register set
H
X
Auto refresh
H
Entry
L
Refresh
Self
refresh
Exit
L
H
COMMAND
CKE
n
/CS
/RAS
/CAS
/WE
DM
BA
0,1
A10/
AP
A11
A9~A0
NOTE
L
L
L
L
L
L
L
L
X
X
OP code
OP code
1,2
1,2
3
3
3
3
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
X
X
Bank active & Row Addr.
Auto precharge
Read &
column
address
H
X
X
V
Row address
disable
L
4
Auto precharge
eable
Auto precharge
disable
Auto precharge
enable
Burst Stop
Bank selection
All banks
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~ A9)
4
L
4
Write &
column
address
H
X
L
H
L
L
X
V
H
Column
Address
(A0 ~ A9)
4,6
H
X
L
H
H
L
X
X
7
5
V
X
L
H
Precharge
H
X
L
L
H
L
X
X
H
L
X
H
X
V
X
X
X
V
X
X
X
V
X
X
Entry
H
L
X
Clock suspend or
active power down
Exit
L
H
X
X
Entry
H
L
L
H
H
H
X
H
L
X
V
X
X
H
X
V
X
V
Precharge power
down mode
Exit
L
H
X
X
DM
H
V
X
8
H
L
X
H
X
H
No operation command
H
X
X
X
Note :
1.
2.
OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
3.
4.
BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
5.
6.
During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
Burst stop command is valid at every burst length.
7.
8.
9.
DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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