參數(shù)資料
型號(hào): HDD32M72D9RPW-10A
廠商: Hanbit Electronics Co.,Ltd.
英文描述: DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register
中文描述: 256MB的DDR SDRAM內(nèi)存模塊(32Mx72bit),基于對(duì)32Mx8,4Banks 8K的參考。,184Pin - DIMM內(nèi)存的鎖相環(huán)
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 418K
代理商: HDD32M72D9RPW-10A
HANBit
HDD32M72D9RPW
URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd.
REV 1.0 (JUNE.2003)
INPUT/OUTPUT Capacitance (V
DD
= 2.5V, V
DDQ
= 2.5V, T
A
= 25
°
C, F = 1MHZ)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance(A0
~ A12, BA0
~ BA1,/RAS,/CAS,/ WE )
C
IN1
-
12
pF
Input Capacitance(CKE0)
C
IN2
-
12
pF
Input Capacitance( /CS0)
C
IN3
-
11
pF
Input Capacitance( CLK0,/CLK0
)
C
IN4
-
12
pF
Data & DQS input/output Capacitance(DQ0~DQ63)
C
OUT1
-
11
PF
Data input/output Capacitance(CB0~CB7)
C
OUT2
-
11
PF
Input Capacitance(DM0~DM8)
C
IN5
-
11
pF
AC Operating Conditions
PARAMETER/ Condition
STMBOL
MIN
MAX
UNIT
NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH
(AC)
V
REF
+ 0.31
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
V
IL
(AC)
V
REF
- 0.31
V
3
Input Differential Voltage, CK and CK inputs
V
ID
(AC)
0.7
V
DDQ
+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
Note
1. V
ID
is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5* V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation.
the AC and DC input specificatims are refation to a V
REF
envelope that has been bandwidth limited 20MHz.
AC Operating TEST Conditions
V
IX
(AC)
0.5*V
DDQ
-0.2
0.5*V
DDQ
+0.2
V
2
PARAMETER
VALUE
UNIT
NOTE
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input Levels(V
IH
/V
IL
)
V
REF
+0.31/V
REF
-0.31
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
V
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