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參數(shù)資料
| 型號： | HDD32M72B9-13A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx72bit）根據(jù)on32Mx8，4Banks，8K的參考。，ECC無緩沖的SO - DIMM |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | HDD32M72B9-13A |
HANBit
HDD32M72B9
URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
Input Slew Rate(for I/O pins)
t
SL(IO)
0.5
0.5
0.5
V/ns
7
Output Slew Rate (x4, x8)
t
SL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
10
Output Slew Rate Matching Ratio(rise to fall)
t
SLMR
0.67
1.5
0.67
1.5
0.67
1.5
Mode register set cycle time
t
MRD
12
15
15
ns
DQ & DM setup time to DQS
t
DS
0.45
0.5
0.5
ns
7,8,9
DQ & DM hold time to DQS
t
DH
0.45
0.5
0.5
ns
7,8,9
DQ & DM input pulse width
t
DIPW
1.75
1.75
1.75
ns
Power down exit time
t
PDEX
6
7.5
7.5
ns
Control & Address input pulse width
t
IPW
2.2
2.2
2.2
ns
Exit self refresh to bank active command
t
XSA
80
75
75
ns
Exit self refresh to non-read command
t
XSNR
75
75
75
ns
4
Exit self refresh to read command
t
XSRD
200
200
200
t
CK
Refresh interval time
T
REFI
7.8
tHPmi
n
-tQHS
tCLmi
n
or
tCHS
7.8
tHPmi
n
-tQHS
tCLmi
n
or
tCHS
7.8
tHPmi
n
-tQHS
tCLmi
n
or
tCHS
us
1
Output DQS valid window
T
QH
ns
5
Clock half period
T
HP
ns
Data hold skew factor
T
QHS
0.55
0.75
0.75
ns
DQS write postamble time
T
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
3
Active to Read with Auto precharge
command
T
RAP
20
20
20
Autoprecharge write recovery + Precharge
time
T
DAL
(tWR/t
CK)
+
(tRP/t
CK)
(tWR/t
CK)
+
(tRP/t
CK)
(tWR/t
CK)
+
(tRP/t
CK)
1CK
11
Notes :
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in
progress, DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are
45% of the period including both the half period jitter (tJIT(HP)) of the PLL
and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
.tIS
.tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDD32M72B9-13B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72D9RPW | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D9RPW-10A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D9RPW-13A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD32M72B9-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72D18RPW | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D9RPW | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D9RPW-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register |
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