參數(shù)資料
型號(hào): HDD32M64F8K
廠商: Hanbit Electronics Co.,Ltd.
英文描述: DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
中文描述: 256MB的DDR SDRAM內(nèi)存模塊(32Mx64bit)根據(jù)on16Mx8,4Banks,4K的參考。,SMM的,
文件頁數(shù): 7/11頁
文件大?。?/td> 171K
代理商: HDD32M64F8K
HANBit
HDD32M64F8K
URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
AC OPERATING TEST CONDITIONS
PARAMETER
VALUE
UNIT
NOTE
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V
Input Levels(V
IH
/V
IL
)
V
REF
+0.35/V
REF
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
V
AC CHARACTERISTICS
(These AC charicteristics were tested on the Component)
DDR200
DDR266A
DDR266B
-10A
-13A
-13B
PARAMETER
SYMBO
L
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
Row cycle time
t
RC
70
65
65
ns
1
Refresh row cycle time
t
RFC
80
75
75
ns
1,2
Row active time
t
RAS
48
120K
45
120K
45
120K
ns
1,2
/RAS to /CAS delay
t
RCD
20
20
20
ns
3
Row precharge time
t
RP
20
20
20
ns
3
Row active to Row active delay
t
RRD
15
15
15
ns
3
Write recovery time
t
WR
2
2
2
t
CK
3
Last data in to Read command
t
CDLR
1
1
1
t
CK
2
Col. address to Col. address delay
t
CCD
1
1
1
t
CK
CL=2.0
10
12
7.5
12
10
12
ns
Clock cycle time
CL=2.5
t
CK
12
7.5
12
7.5
12
ns
相關(guān)PDF資料
PDF描述
HDD32M64F8K-10A DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
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HDD32M64F8K-13B DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
HDD32M64F8 DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM,
HDD32M64F8-10A DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM,
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