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參數(shù)資料
| 型號： | HDD32M64F8-13A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx64bit），在32Mx8，4Banks，8K的參考依據(jù)。，SMM的， |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 208K |
| 代理商： | HDD32M64F8-13A |
HANBit
HDD32M64F8
URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)
Exit self refresh to write command
t
XSW
116
95
ns
Exit self refresh to bank active command
t
XSA
80
75
75
ns
Exit self refresh to read command
t
XSR
200
200
200
Cycle
Refresh interval time
t
REF
15.6
15.6
15.6
us
1
Output DQS valid window
t
QH
0.35
0.35
0.35
t
CK
DQS write postamble time
t
WPST
0.25
0.25
0.25
t
CK
4
Notes :
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on t
.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t
RCD
satisfied after this command.
5. For registered DIMMs, t
and t
are
≥
45% of the period including both the half period jitter (t
JIT
(HP) ) of the PLL and the half jitter due to
crosstalk (t
JIT
(crosstalk) ) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
Δ
t
IS
Δ
t
IH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase t
/t
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
(V/ns)
0.5
0.4
0.3
This derating table is used to increase t
/t
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Δ
t
IS
(ps)
0
+75
+150
Δ
t
IH
(ps)
0
+75
+150
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
±
280
This derating table is used to increase t
DS
/t
DH
in the case where the input level is flat below V
REF
±
310mV for a duration of up to 2ns.
Δ
t
DS
(ps)
+50
Δ
t
DH
(ps)
+50
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
(ns/V)
0
±
0.25
±
0.5
Δ
t
DS
(ps)
0
+50
+100
Δ
t
DH
(ps)
0
+50
+100
This derating table is used to increase t
/t
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. t
CK
is actual to the system clock cycle time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD32M64F8-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, |
| HDD32M64F8K | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD32M64F8K-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD32M64F8K-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD32M64F8K-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
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