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參數(shù)資料
| 型號： | HDD32M64F8-10A |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx64bit），在32Mx8，4Banks，8K的參考依據(jù)。，SMM的， |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 208K |
| 代理商： | HDD32M64F8-10A |
HANBit
HDD32M64F8
URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)
COMMAND TRUTH TABLE
(V=VALID, X=DO
ν
￠
T CARE, H=LOGIC HIGH, L=LOGIC LOW)
COMMAND
Extended MRS
Mode register set
Auto refresh
CKE
n-1
CKE
n
/CS
/RAS
/CAS
/WE
DM
BA
0,1
A10/
AP
A11
A9~A0
NOTE
1,2
1,2
3
3
3
3
Register
Register
H
H
X
X
H
L
L
L
L
L
L
L
L
L
X
X
OP code
OP code
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
refresh
Exit
L
H
X
X
Bank active & Row Addr.
Auto
disable
column
address
eable
Auto
disable
column
address
enable
Burst Stop
H
X
X
V
Row address
precharge
L
4
Read &
Auto
precharge
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~ A9)
4
precharge
H
L
4
Write &
Auto
precharge
H
X
L
H
L
L
X
V
H
Column
Address
(A0 ~ A9)
4,6
H
X
L
H
H
L
X
X
7
5
8
Bank selection
All banks
V
X
L
H
Precharge
H
X
L
L
H
L
X
X
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
Exit
L
H
X
X
Entry
H
L
X
Precharge power
down mode
Exit
L
H
X
X
DM
H
V
X
H
L
X
H
X
H
No operation command
H
X
X
X
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD32M64F8-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, |
| HDD32M64F8-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, |
| HDD32M64F8K | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD32M64F8K-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD32M64F8K-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
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