參數(shù)資料
型號(hào): HDD32M64B8
廠商: Hanbit Electronics Co.,Ltd.
英文描述: DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
中文描述: 256MB的DDR SDRAM內(nèi)存模塊(32Mx64bit)根據(jù)on32Mx8,4Banks,8K的參考。,SO - DIMM插槽
文件頁(yè)數(shù): 9/11頁(yè)
文件大?。?/td> 173K
代理商: HDD32M64B8
HANBit
HDD32M64B8
URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on t
DQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
SIMPLIFIED TRUTH TABLE
COMMAND
CK
E
n-1
H
H
CK
E
n
X
X
H
L
/CS
/R
A
S
L
L
/C
A
S
L
L
/WE
DM
BA
0,1
A10/
AP
A11
A9~A0
NOTE
Register
Register
Extended MRS
Mode register set
Auto refresh
L
L
L
L
X
X
OP code
OP code
1,2
1,2
3
3
3
3
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
refresh
Exit
L
H
X
X
Bank active & row addr.
Auto
disable
column
address
Auto precharge eable
Auto
disable
column
address
enable
Burst Stop
Bank selection
Precharg
e
All banks
H
X
X
V
Row address
precharge
L
4
Read &
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~A9)
4
precharge
H
L
4
Write &
Auto
precharge
H
X
L
H
L
L
X
V
H
Column
Address
(A0 ~ A9)
4,6
H
X
L
H
H
L
X
X
7
5
8
V
X
L
H
H
X
L
L
H
L
X
X
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
Exit
L
H
X
X
Entry
H
L
X
Precharge power
down mode
Exit
L
H
X
X
DM
H
V
X
H
L
X
H
X
H
X
H
No operation command
H
X
X
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
相關(guān)PDF資料
PDF描述
HDD32M64B8-10A DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
HDD32M64B8-13A DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
HDD32M64B8-13B DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
HDD32M64F8K DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
HDD32M64F8K-10A DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
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