參數(shù)資料
型號： HDD16M72D9W-10A
廠商： Hanbit Electronics Co.,Ltd.
英文描述： DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
中文描述： DDR SDRAM內(nèi)存模塊128Mbyte（16Mx72bit），基于對16Mx8，4Banks 4K的參考。，184Pin，與無緩沖ECC內(nèi)存
文件頁數(shù)： 7/11頁
文件大?。?/td> 163K
代理商： HDD16M72D9W-10A
HANBit
HDD16M72D9W
URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (November.2002)
AC Timming Parameters & Specifications
(These AC charicteristics were tested on the Component)
DDR200
DDR266A
DDR266B
-10A
-13A
-13B
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
Row cycle time
t
RC
70
65
65
ns
1
Refresh row cycle time
t
RFC
80
75
75
ns
1,2
Row active time
t
RAS
48
120K
45
120K
45
120K
ns
1,2
/RAS to /CAS delay
t
RCD
20
20
20
ns
3
Row precharge time
t
RP
20
20
20
ns
3
Row active to Row active delay
t
RRD
15
15
15
ns
3
Write recovery time
t
WR
15
15
15
t
CK
3
Last data in to Read command
t
CDLR
1
1
1
t
CK
2
Col. address to Col. address delay
t
CCD
1
1
1
t
CK
CL=2.0
10
12
7.5
12
10
12
ns
Clock cycle time
CL=2.5
t
CK
12
7.5
12
7.5
12
ns
Clock high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS-out access time from CK/CK
t
DQSCK
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
t
AC
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
t
DQSQ
-
+0.6
-
+0.5
-
+0.5
ns
Read Preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
Data out high impedence time from CK-/CK
t
HZQ
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
2
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
0
0
ns
3
DQS-in hold time
t
WPREH
0.25
0.25
0.25
t
CK
DQS-in falling edge to CK rising-setup time
t
DSS
0.2
0.2
0.2
t
CK
DQS-in falling edge to CK rising hold time
t
DSH
0.2
0.2
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Address and Control Input setup time
t
IS
1.1
0.9
0.9
ns
Address and Control Input hold time
t
IH
1.1
0.9
0.9
ns
Mode register set cycle time
t
MRD
16
15
15
ns
DQ & DM setup time to DQS
t
DS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
t
DH
0.6
0.5
0.5
ns
DQ & DM input pulse width
t
DIPW
2
1.75
1.75
ns
Power down exit time
t
PDEX
10
7.5
7.5
ns
Exit self refresh to write command
t
XSW
116
95
ns
Exit self refresh to bank active command
t
XSA
80
75
75
ns
Exit self refresh to read command
t
XSR
200
200
200
Cycle
Refresh interval time
t
REF
15.6
15.6
15.6
us
1
Output DQS valid window
t
QH
-
-
-
-
-
-
t
CK
DQS write postamble time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
4
相關PDF資料
PDF描述
HDD16M72D9W-13A DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-13B DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD32M64B8 DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
HDD32M64B8-10A DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
HDD32M64B8-13A DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
相關代理商/技術參數(shù)
參數(shù)描述
HDD16M72D9W-13A 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-13B 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD2.5IN 制造商:AAEON Technology Inc 功能描述:HTS548080M9AT00 80GB/ - Bulk
HDD-2187 制造商:Toshiba America Electronic Components 功能描述:- Bulk
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