參數(shù)資料
型號： HDD16M72D9RPW-13B
廠商： Hanbit Electronics Co.,Ltd.
英文描述： DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
中文描述： DDR SDRAM內(nèi)存模塊128Mbyte（16Mx72bit），基于對16Mx8，4Banks 4K的參考。，184Pin - DIMM內(nèi)存的鎖相環(huán)
文件頁數(shù)： 7/10頁
文件大小： 349K
代理商： HDD16M72D9RPW-13B
HANBit
HDD16M72D9RPW
URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (November.2002)
AC Timming Parameters & Specifications
(These AC charicteristics were tested on the Component)
DDR200
DDR266A
DDR266B
-10A
-13A
-13B
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
Row cycle time
t
RC
t
RFC
t
RAS
t
RCD
t
RP
t
RRD
t
WR
t
CDLR
t
CCD
70
65
65
ns
1
Refresh row cycle time
80
75
75
ns
1,2
Row active time
48
120K
45
120K
45
120K
ns
1,2
/RAS to /CAS delay
20
20
20
ns
3
Row precharge time
20
20
20
ns
3
Row active to Row active delay
15
15
15
ns
3
Write recovery time
2
2
2
t
CK
t
CK
t
CK
ns
3
Last data in to Read command
1
1
1
2
Col. address to Col. address delay
1
1
1
CL=2.0
10
12
7.5
12
10
12
Clock cycle time
CL=2.5
t
CK
12
7.5
12
7.5
12
ns
Clock high level width
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
HZQ
t
DQSS
t
WPRES
t
WPREH
t
DSS
t
DSH
t
DQSH
t
DQSL
t
DSC
t
IS
t
IH
t
MRD
t
DS
t
DH
t
DIPW
t
PDEX
t
XSW
t
XSA
t
XSR
t
REF
t
QH
t
WPST
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
t
CK
ns
Clock low level width
0.45
0.55
0.45
0.55
0.45
0.55
DQS-out access time from CK/CK
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
Output data access time from CK/CK
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
-
+0.6
-
+0.5
-
+0.5
ns
Read Preamble
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
t
CK
ns
Read Postamble
0.4
0.6
0.4
0.6
0.4
0.6
Data out high impedence time from CK-/CK
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
2
CK to valid DQS-in
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
ns
DQS-in setup time
0
0
0
3
DQS-in hold time
0.25
0.25
0.25
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
ns
DQS-in falling edge to CK rising-setup time
0.2
0.2
0.2
DQS-in falling edge to CK rising hold time
0.2
0.2
0.2
DQS-in high level width
0.35
0.35
0.35
DQS-in low level width
0.35
0.35
0.35
DQS-in cycle time
0.9
1.1
0.9
1.1
0.9
1.1
Address and Control Input setup time
1.1
0.9
0.9
Address and Control Input hold time
1.1
0.9
0.9
ns
Mode register set cycle time
16
15
15
ns
DQ & DM setup time to DQS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
0.6
0.5
0.5
ns
DQ & DM input pulse width
2
1.75
1.75
ns
Power down exit time
10
10
10
ns
Exit self refresh to write command
116
95
ns
Exit self refresh to bank active command
80
75
75
ns
Exit self refresh to read command
200
200
200
Cycle
Refresh interval time
15.6
15.6
15.6
us
1
Output DQS valid window
0.35
0.35
0.35
t
CK
t
CK
DQS write postamble time
0.25
0.25
0.25
4
相關(guān)PDF資料
PDF描述
HDD16M72D9W DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-10A DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-13A DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-13B DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD32M64B8 DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDD16M72D9W 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-10A 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-13A 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD16M72D9W-13B 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
HDD2.5IN 制造商:AAEON Technology Inc 功能描述:HTS548080M9AT00 80GB/ - Bulk
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