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參數(shù)資料
| 型號： | HDD16M64D8W-13B |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., DIMM, |
| 中文描述： | DDR SDRAM內(nèi)存模塊128Mbyte（16Mx64bit）根據(jù)on16Mx8，4Banks，4K的參考。，內(nèi)存， |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 211K |
| 代理商： | HDD16M64D8W-13B |
HANBit
HDD16M64D8W
URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)
This derating table is used to increase t
/t
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
(V/ns)
0.5
0.4
0.3
This derating table is used to increase t
/t
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Δ
t
IS
(ps)
0
+75
+150
Δ
t
IH
(ps)
0
+75
+150
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
±
280
This derating table is used to increase t
DS
/t
DH
in the case where the input level is flat below V
REF
±
310mV for a duration of up to 2ns.
Δ
t
DS
(ps)
+50
Δ
t
DH
(ps)
+50
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
(ns/V)
0
±
0.25
±
0.5
Δ
t
DS
(ps)
0
+50
+100
Δ
t
DH
(ps)
0
+50
+100
This derating table is used to increase t
/t
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. t
CK
is actual to the system clock cycle time.
COMMAND TRUTH TABLE
(V=VALID, X=DO
ν
￠
T CARE, H=LOGIC HIGH, L=LOGIC LOW)
COMMAND
Extended MRS
Mode register set
Auto refresh
CKE
n-1
CKE
n
/CS
/RAS
/CAS
/WE
DM
BA
0,1
A10/
AP
A11
A9~A0
NOTE
1,2
1,2
3
3
3
3
Register
Register
H
H
X
X
H
L
L
L
L
L
L
L
L
L
X
X
OP code
OP code
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
refresh
Exit
L
H
X
X
Bank active & Row Addr.
Auto
disable
column
address
eable
Auto
disable
column
address
enable
Burst Stop
H
X
X
V
Row address
precharge
L
4
Read &
Auto
precharge
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~ A9)
4
precharge
H
L
4
Write &
Auto
precharge
H
X
L
H
L
L
X
V
H
Column
Address
(A0 ~ A9)
4,6
H
X
L
H
H
L
X
X
7
5
Bank selection
All banks
V
X
L
H
Precharge
H
X
L
L
H
L
X
X
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
Entry
H
L
X
Clock suspend or
active power down
Exit
L
H
X
X
Precharge power
down mode
Entry
H
L
X
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD16M64F8 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD16M64F8-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD16M64F8-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD16M64F8-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, |
| HDD16M72D9RPW | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register |
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