參數(shù)資料
型號： HDD128M72D18RPW-13B
廠商： Hanbit Electronics Co.,Ltd.
英文描述： DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
中文描述： DDR SDRAM內(nèi)存模塊1024Mbyte（128Mx72bit），在64Mx8，4Banks，8K的參考依據(jù)。，184Pin與鎖相環(huán)內(nèi)存
文件頁數(shù)： 8/14頁
文件大?。?/td> 459K
代理商： HDD128M72D18RPW-13B
HANBit
HDD128M72D18RPW
URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 1.0 (January. 2005)
Address and Control Input hold time(Slow)
t
IH
0.8
1.0
1.0
ns
i, 6~9
Data-out high impedence time from CK/CK
t
HZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Data-out low impedence time from CK/CK
t
LZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Input Slew Rate(for input only pins)
t
SL(IO)
0.5
0.5
0.5
ns
Input Slew Rate(for I/O pins)
t
SL(O)
0.5
0.5
0.5
t
CK
Output Slew Rate(x4,x8)
t
SL(O)
1.0
4.5
1.0
4.5
1.0
4.5
t
CK
Output Slew Rate(x16)
t
SL(O)
0.7
5
0.7
5
0.7
5
Output Slew Rate Matching Ratio(rise to fall)
t
SLMR
0.67
1.5
0.67
1.5
0.67
1.5
Mode register set cycle time
t
MRD
12
15
15
ns
DQ & DM setup time to DQS
t
DS
0.45
0.5
0.5
ns
j, k
DQ & DM hold time to DQS
t
DH
0.45
0.5
0.5
ns
j, k
Control & Address input pulse width
t
IPW
2.2
2.2
2.2
ns
8
DQ & DM input pulse width
t
DIPW
1.75
1.75
1.75
ns
8
Power down exit time
t
PDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
t
XSNR
75
75
75
ns
Exit self refresh to read command
t
XSRD
200
200
200
t
CK
Refresh interval time
t
REFI
7.8
t
HP
7.8
t
HP
7.8
t
HP
ns
4
Output DQS valid window
t
QH
-t
QHS
-
-t
QHS
-
-t
QHS
-
ns
11
Clock half period
t
HP
t
CLmin
or
t
CHmin
-
t
CLmin
or
t
CHmin
-
t
CLmin
or
t
CHmin
-
ns
10,11
Data hold skew factor
t
QHS
0.55
0.75
0.75
ns
11
DQS write postamble time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
2
Active to Read with Auto precharge
command
t
RAP
18
20
20
Autoprecharge write recovery +
Precharge time
t
DAL
(t
WR
/t
CK
)+
(t
RP
/t
CK
)
(t
WR
/t
CK
)+
(t
RP
/t
CK
)
(t
WR
/t
CK
)+
(t
RP
/t
CK
)
t
CK
13
Notes :
Maximum burst refresh of 8.
t
HZQ
transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving.
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low)
applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time,
depending on t
DQSS.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
相關(guān)PDF資料
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參數(shù)描述
HDD128M72D18RPW-16B 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
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