參數(shù)資料
型號(hào): HD74LV2GT14AUSE
元件分類: 門電路
英文描述: LV/LV-A/LVX/H SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8
封裝: SSOP-8
文件頁數(shù): 1/10頁
文件大?。?/td> 87K
代理商: HD74LV2GT14AUSE
Rev.2.00, Oct.16.2003, page 1 of 9
HD74LV2GT14A
Triple Inverters with Schmitt-trigger Inputs /
CMOS Logic Level Shifter
REJ03D0141–0200Z
(Previous ADE-205-666A (Z))
Rev.2.00
Oct.16.2003
Description
The HD74LV2GT14A has triple inverters with Schmitt-trigger inputs in an 8 pin package. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic
5.0 V CMOS logic (@V
CC
= 5.0 V)
1.8 V or 2.5 V CMOS logic
3.3 V CMOS logic (@V
CC
= 3.3 V)
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV2GT14AUSE SSOP-8 pin
TTP-8DBV
US
E (3,000 pcs/reel)
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