參數(shù)資料
型號(hào)： HD74LV165A
廠商： Hitachi,Ltd.
英文描述： Parallel-Load 8-bit Shift Register(并行載入8位移位寄存器)
中文描述： 并聯(lián)負(fù)載8位的移位寄存器（并行載入8位移位寄存器）
文件頁(yè)數(shù)： 1/17頁(yè)
文件大?。?/td> 75K
代理商： HD74LV165A
HD74LV165A
Parallel-Load 8-bit Shift Register
ADE-205-267 (Z)
1st Edition
March 1999
Description
The HD74LV165A is 8-bit serial shift register shifts data from Q
A
to Q
H
when clocked. Parallel inputs to
each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a
complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and high enables the other clock input.
Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the
Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register
independent of the state of the clock.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Output current
±
6 mA (@V
CC
= 3.0 V to 3.6 V),
±
12 mA (@V
CC
= 4.5 V to 5.5 V)
相關(guān)PDF資料
PDF描述
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