參數(shù)資料
型號(hào): HD74HCT237
廠商: Hitachi,Ltd.
英文描述: 3-to-8-line Decoder/Demultiplexer with Address Latch
中文描述: 3至8線解碼器/解復(fù)用器的地址鎖存器
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 57K
代理商: HD74HCT237
HD74HCT237
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a
transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are
provided to facilitate the demultiplexing, cascading, and chip-selecting functions.
The demultiplexing function is accomplished by using the Address inputs to select the desired device
output, and then by using one of the Chip Select as a data input while holding the other one active.
The HD74HCT237 is the noninverting version of the HD74HCT137.
Features
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(A, B, C to Y) = 23 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
相關(guān)PDF資料
PDF描述
HD74HCT238 Replaced by SN54ALS373A : Octal D-Type Transparent Latches with 3-state Outputs 20-CDIP -55 to 125
HD74HCT240 Octal Buffers/Line Drivers/Line Receivers(with inverted 3-state outputs)
HD74HCT241 Replaced by SN54ALS373A : Octal D-Type Transparent Latches with 3-state Outputs 20-LCCC -55 to 125
HD74HCT242 Quad. Bus Transceivers (with 3-state outputs)
HD74HCT243 Quad. Bus Transceivers (with 3-state outputs)
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