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參數(shù)資料
| 型號(hào)： | HD74HC595 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8-bit Shift Register/Latch (with 3-state outputs) |
| 中文描述： | 8位的移位寄存器/鎖存（3態(tài)輸出） |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | HD74HC595 |
HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register and the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect
both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
Features
High Speed Operation: t
pd
(RCK to Q) = 17 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads (Q
A
to Q
H
outputs)
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
Function Table
RCK
SCK
SCLR
G
Function
X
X
X
H
Q
A
to Q
H
high impedance
Shift register cleared Q
H
’ = L
Shift register clocked Q
n
= Q
n – 1
, Q
A
= SER
Contents of shift register transferred to output latches
X
X
L
X
X
H
X
X
H
X
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