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參數(shù)資料
| 型號(hào)： | HD74CDC857 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3/2.5-V Phase-lock Loop Clock Driver |
| 中文描述： | 3.3/2.5-V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 54K |
| 代理商： | HD74CDC857 |
HD74CDC857
8
Electrical Characteristics
Item
Symbol
Min
Typ
*1
Max
Unit
Test Conditions
Input clamp
voltage
CLK,
CLK
FBIN,
FBIN
, G
V
IK
—
—
–1.2
V
I
I
= –18 mA, V
DDQ
= 2.3 V
Output voltage
V
OH
V
CC
–0.2 —
1.95
—
V
I
OH
= –100
μ
A, V
CC
= 2.3 to 2.7 V
I
OH
= –8 mA, V
CC
= 2.3 V
I
OH
= –16 mA, V
CC
= 2.3 V
I
OL
= 100
μ
A, V
CC
= 2.3 to 2.7 V
I
OL
= 8 mA, V
CC
= 2.3 V
I
OL
= 16 mA, V
CC
= 2.3 V
V
I
= 0 V to 2.7 V, V
DDQ
= 2.7 V
—
—
1.70
—
—
V
OL
—
—
0.2
—
—
0.35
—
—
0.55
Input current
I
I
C
I
—
—
±
10
μ
A
Input capacitance
Note:
1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
—
—
4
pF
Switching Characteristics
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Cycle to cycle jitter
–100
—
100
ps
See figure 2
Phase error time
t
(phase error)
t
sk (o)
t
sk (diff)
–150
—
150
ps
See figure 2, 3, 4
Output skew
—
—
200
ps
See figure 2
Differential clock skew
–100
—
100
ps
See figure 2
Duty cycle
45
—
55
%
See figure 2
Output impedance
Z
O
f
CLK
—
25
—
MHz See figure 2, AV
CC
= 2.5
±
0.2 V
See figure 2, AV
= 2.5
±
0.2 V
or AV
CC
= 3.3
±
0.3 V
V/ns See figure 2
See figure 2
Clock frequency
100
—
150
*1
130
—
150
*1
Slew rate
1.2
—
—
Stabilization time
Note:
1. 200 MHz (Max) ver. will be available by 4Q/’99.
—
—
0.1
ms
See figure 2, 3
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