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Section 9
9.1
Ethernet Controller (EtherC)
....................................................................... 371
Overview............................................................................................................................ 371
9.1.1
Features................................................................................................................. 371
9.1.2
Configuration........................................................................................................ 372
9.1.3
Pin Configuration.................................................................................................. 374
9.1.4
Ethernet Controller Register Configuration.......................................................... 375
Register Descriptions......................................................................................................... 376
9.2.1
EtherC Mode Register (ECMR)............................................................................ 376
9.2.2
Receive Frame Length Register (RFLR).............................................................. 379
9.2.3
EtherC Status Register (ECSR)............................................................................ 380
9.2.4
EtherC Status Interrupt Permission Register (ECSIPR)....................................... 381
9.2.5
PHY Interface Register (PIR)............................................................................... 382
9.2.6
PHY Interface Status Register (PSR) ................................................................... 383
9.2.7
MAC Address High Register (MAHR)................................................................ 384
9.2.8
MAC Address Low Register (MALR) ................................................................. 385
9.2.9
Tx Retry Over Counter Register (TROCR).......................................................... 386
9.2.10 Collision Detect Counter Register (CDCR).......................................................... 387
9.2.11 Lost Carrier Counter Register (LCCR)................................................................. 388
9.2.12 Carrier Not Detect Counter Register (CNDCR)................................................... 389
9.2.13 Illegal Frame Length Counter Register (IFLCR).................................................. 390
9.2.14 CRC Error Frame Counter Register (CEFCR)..................................................... 391
9.2.15 Frame Receive Error Counter Register (FRECR ) ............................................... 392
9.2.16 Too-Short Frame Receive Counter Register (TSFRCR)...................................... 393
9.2.17 Too-Long Frame Receive Counter Register (TLFRCR )..................................... 394
9.2.18 Residual-Bit Frame Counter Register (RFCR)..................................................... 395
9.2.19 Multicast Address Frame Counter Register (MAFCR)........................................ 396
Operation............................................................................................................................ 397
9.3.1
Transmission......................................................................................................... 397
9.3.2
Reception.............................................................................................................. 399
9.3.3
MII Frame Timing................................................................................................ 401
9.3.4
Accessing MII Registers....................................................................................... 403
9.3.5
Magic Packet Detection.................................................................................... 406
9.3.6
CPU Operating Mode and Ethernet Controller Operation.................................... 407
Connection to PHY-LSI..................................................................................................... 408
9.2
9.3
9.4
Section 10 Ethernet Controller Direct Memory Access Controller
(E-DMAC)
........................................................................................................ 411
10.1 Overview............................................................................................................................ 411
10.1.1 Features................................................................................................................. 411
10.1.2 Configuration........................................................................................................ 412
10.1.3 Descriptor Management System........................................................................... 413
10.1.4 Register Configuration.......................................................................................... 413
10.2 Register Descriptions......................................................................................................... 415