參數(shù)資料
型號: HD61830A00H
廠商: Hitachi,Ltd.
英文描述: LCDC (LCD Timing Controller)
中文描述: LCDC(LCD定時控制器)
文件頁數(shù): 40/43頁
文件大?。?/td> 173K
代理商: HD61830A00H
HD61830/HD61830B
40
2. ROM/RAM read timing
T
1
T
2
T
3
T
1
(
*
1)
a
t
DCE
t
HCE
(
*
2)
t
DCE
t
HCE
t
DCE
t
HCE
2.4V
0.6V
b
a
(
*
1)
(
*
2)
0.6V
t
DMA
t
HMA
Address for upper screen
2.4V
0.6V
t
SMD
t
DMA
t
HMA
t
DMA
t
HMA
t
HMA
(
*
3)
t
HMD
t
SMD
t
HMD
t
SMD
t
HMD
2.2V
0.8V
Data for the upper screen
(
*
4)
Address for
the lower screen
Data for
the lower screen
t
HRD
t
SRD
t
HRD
t
SRD
2.2V
0.8V
Data for the upper screen
Data for the
lower screen
Invalid data
CR
CE
OE
MA0–MA15
MD0–MD7
(input)
RD0–RD7
*1
This figures shows the timing for H
p
= 8.
For H
= 7, time shown by “b” becomes zero. For H
p
= 6, time shown by “a” and “b”
become zero.
Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of H
p
= 8,
H
p
= 7, or H
p
= 6 respectively.
The waveform for instructions with memory read is shown with a dash line. In other cases,
the waveform shown with a solid line is generated.
When an instruction with RAM read/write is executed, the value of cursor address is
output. In other cases, invalid data is output.
When an instruction with RAM read is executed, HD61830B latches the data at this timing.
In other cases, this data is invalid.
3. Test load circuit
*2
*3
*4
V
CC
R
L
D2
D3
D4
D1
C
R
Test point
R
L
= 2.4 k
R = 11 k
C = 50 pF (C includes jig capacitance)
Diodes D1 to D4 1S2074
H
相關PDF資料
PDF描述
HD61830 LCDC (LCD Timing Controller)
HD61830B LCDC (LCD Timing Controller)
HD61830B00H LCDC (LCD Timing Controller)
HD6301X0 CMOS MCU
HD6301X0CP CMOS MCU
相關代理商/技術參數(shù)
參數(shù)描述
HD61830B 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCDC (LCD Timing Controller)
HD61830B00 制造商:HITCHI 功能描述:
HD61830B00H 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCDC (LCD Timing Controller)
HD61945MP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop
HD6301V0P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller