HD404459 Series
8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
$00A
$00B
10
11
Timer read register B lower
Timer read register B upper
(TRBL)
(TRBU)
R
R
Timer write register B lower
Timer write register B upper
(TWBL)
(TWBU)
W
W
14
15
$00E
$00F
Timer read register C lower
Timer read register C upper
(TRCL)
(TRCU)
R
R
Timer write register C lower
Timer write register C upper
(TWCL)
(TWCU)
W
W
17
18
$011
$012
Timer read register D lower
Timer read register D upper
(TRDL)
(TRDU)
R
R
Timer write register D lower
Timer write register D upper
(TWDL)
(TWDU)
W
W
0
64
80
512
768
960
$000
$040
$050
$200
$300
$3C0
1023
$3FF
*
Note:
*
Two registers are mapped
onto the same address
($00A, $00B, $00E, $00F,
$011, and $012).
R:
W:
R/W:
Read only
Write only
Read/write
Interrupt control bits area
Port mode register A
Serial mode register A
Serial data register lower
Serial data register upper
Timer mode register A
Timer mode register B1
Miscellaneous register
Timer mode register C1
Timer mode register D1
Timer mode register B2
Timer mode register C2
Timer mode register D2
Comparator control register
Comparator enable register
Wakeup select register
Port mode register B
Port mode register C
Detection edge select register 1
Detection edge select register 2
Serial mode register B
System clock select register 1
System clock select register 2
Port D
0
to D
3
DCR
Port D
4
to D
7
DCR
Port D
8
to D
9
DCR
Port R
0
DCR
Port R
1
DCR
Port R
2
DCR
Port R
3
DCR
Port R
4
DCR
Port R
5
DCR
Port R
6
DCR
Port R
7
DCR
Port R
8
DCR
Port R
9
DCR
(PMRA)
(SMRA)
(SRL)
(SRU)
(TMA)
(TMB1)
(TRBL/TWBL)
(TRBU/TWBU)
(MIS)
(TMC1)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TRDL/TWDL)
(TRDU/TWDU)
(TMB2)
(TMC2)
(TMD2)
(CCR)
(CER)
(WSR)
(PMRB)
(PMRC)
(ESR1)
(ESR2)
(SMRB)
(SSR1)
(SSR2)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(DCR9)
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
W
R/W
R
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Register flag area
Not used
Not used
Not used
RAM-mapped register
Memory register (MR)
HD404458
Data (432 digits)
HD404459, HD4074459
Data (688 digits)
Stack (64 digits)
Not used
Not used
Figure 2 RAM Memory Map