參數(shù)資料
型號: HD404369S
廠商: Hitachi,Ltd.
英文描述: 4-bit HMCS400-Series microcomputer
中文描述: 4位HMCS400系列微機
文件頁數(shù): 65/115頁
文件大小: 452K
代理商: HD404369S
HD404369 Series
65
Timer C Operations:
Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C (TMC: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is
shown in figure 48. Program run can be controlled by initializing timer C by software before it reaches
$FF.
Timer output operation: The PWM output modes can be selected for timer C by setting port mode
register A (PMRA: $004).
By selecting the timer output mode, pin R0
3
/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C (TMC:
$00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in
figure 49.
$FF + 1
$00
Timer C
count value
Overflow
Time
CPU
operation
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Normal
operation
Reset
Figure 48 Watchdog Timer Operation Flowchart
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