參數(shù)資料
型號: HD404369F
廠商: Hitachi,Ltd.
英文描述: 4-bit HMCS400-Series microcomputer
中文描述: 4位HMCS400系列微機
文件頁數(shù): 77/115頁
文件大小: 452K
代理商: HD404369F
HD404369 Series
77
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.
Notes on Use:
Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.
Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the
SCK
pin is at 1, that is, after executing the input instruction to port R0.
STS wait state
(octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(octal counter = 000)
Transfer state
(octal counter
000)
MCU reset
00
SMR write
04
STS instruction
01
Transmit clock
02
8 transmit clocks
03
STS instruction (IFS 1)
05
SMR write (IFS 1)
06
External clock mode
STS wait state
(octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(octal counter = 000)
Transfer state
(octal counter
000)
SMR write
14
STS instruction
11
Transmit clock
12
15
STS instruction (IFS 1)
8 transmit clocks
13
Internal clock mode
Continuous clock output state
(PMRA 0, 1 = 0, 0)
SMR write
18
Transmit clock 17
16
Note: Refer to the Operating States section for the corresponding encircled numbers.
MCU reset
10
SMR write (IFS 1)
Figure 59 Serial Interface State Transitions
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